The logic used to calculate tick count in
_udelay() was always giving Zero. Updated
the logic to make it work across QCA boards.
Change-Id: Iebc5905003ad99e66b299de3beabb80ce40ce710
Signed-off-by: Aditya Kumar Patra S <apatr@codeaurora.org>
Since smem structure is differnt for ipq8064 and ipq4019, Updated smem
structure table qca_platform to match both the SOCs.
Change-Id: Ia80fc3f8e4460785ed742b719617e6bcfd99ea27
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
Only ipq40xx and ipq807x specific functionalities were
available in common SMEM. Made ipq806x specific changes
so that all QCA platforms can use this.
Change-Id: I00fc9c9ba8e2545d665c9791849d82e0ab5d974a
Signed-off-by: Aditya Kumar Patra S <apatr@codeaurora.org>
This change eliminates the use of gboard_param
variable. Subsequent changes will make use of
dts.
Change-Id: Ic79a72c4fa1b86e864b55306a32c110bcfbc9184
Signed-off-by: Akila N <akilan@codeaurora.org>
Added device tree based IPQ common GPIO driver.
Updated device tree with uart_gpio data.
Change-Id: I4752609a766716d3bdd97f6ca1c1c20ffa3caa47
Signed-off-by: Aditya Kumar Patra S <apatr@codeaurora.org>
Added ipq806x timer information to common timer driver.
Updated qcom timer comon driver for ipq806x support.
Change-Id: I1a28ef362bc4161af38d1065b3c4b848ef4ad0d1
Signed-off-by: Aditya Kumar Patra S <apatr@codeaurora.org>
Moving cmd_bootqca.c from architecture specific common directory to
board specific common directory.
Change-Id: I453abeb554572bf2363a959e7dbe32efcf7dbac6
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
Added dts and initial board support for ipq806x.
Change-Id: I33992413905a0399ea3d6dfbd606c8e7ec30b6bf
Signed-off-by: Aditya Kumar Patra S <apatr@codeaurora.org>
Set mtdids environment variable based on the boot flash so that right
set of mtdids is patched to kernel device tree.
Change-Id: If2f063e51a6bb73f3e8197fb133e0399b0b4df18
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
Fixed warnings for both ipq807x and ipq40xx
builds.
Change-Id: I69accebf525ee52f470335a14474378f5e7f65b0
Signed-off-by: Saravanan Jaganathan <sjaganat@codeaurora.org>
SMC calls are common for IPQ807x, IPQ40xx hence moving it to
common folder
Change-Id: I3d6564ad51ebe396f85cedbf41374374f40865c6
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
dtbs are made as .o
a table specifying their machid and address is added
the dtbs and header are added to u-boot image in a seperate section
dtb will be chosen based on machid detected from SMEM
Change-Id: I50ac5b56da3a431c1a75cb9fc113fafaedbc09b8
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
The SMEM is used for all the platforms like ipq40xx and ipq807x.
So moving this into a common place to use all qcom platforms.
Change-Id: I04f0bf0e7aad0eae71024d734d8049a3470d510d
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
u-boot and dtb are seperate images. This patch combines them as
single ELF image.
Change-Id: Ib3c72c26844ffd4fd8489d0595c243a15434802e
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
GCNT is already enabled by SBL, hence this could be avoided
in u-boot.
Change-Id: I207f0085f015ea7c5e80d8d20c0af95e498a9565
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
changing timer load value to 64 bit data type
Change-Id: I09a35980e5ac15fdfdae3896e7f04ef87b403894
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
On these platforms we have many cases of boards that enable device model
and GPIO support but do not enable OF_CONTROL and pass in a device tree
with the binary. We need to bring in the platform data here as well.
Tested on Beaglebone Black.
Reported-by: Robert Nelson <robertcnelson@gmail.com>
Reported-by: Francisco Aguerre <franciscoaguerre@gmail.com>
Reported-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
For some board designs, it might be useful to switch the DC-DC
clock source to something else rather the default 24 MHz, e.g.
for EMI reasons.
For this, override the mxs_power_setup_dcdc_clocksource function
in your board support files.
Example:
void mxs_power_setup_dcdc_clocksource(void)
{
mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ);
}
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
