This patch makes mmc driver dcache aware to keep
the mmc functionality intact, with or without dcache
is enabled.
flush_cache used here does both clean and invalidate
cache thus preventing data loss during unaligned access,
if any.
Change-Id: I0910bd17678d3855bba27e9f8f7c08606774b28d
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This patch adds the support on nand driver to work
when dcache is on.
flush_dcache_range will do both clean and invalidate.
To avoid any data loss when an un-aligned buffer used
in RX path, before giving buffer to bam and after bam
updates the data in buffer, buffer will be flushed.
Change-Id: Ib38d68726efe1692ae94c2be1af61cf29d1c2e50
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Some of the newer nand parts can have bit flips in an erased
page due to the process technology used. In this case, ipq
nand controller is not able to identify that page as an erased
page. In case of bitflips, the ECC engine tries to correct the
data and then it generates the uncorrectable error. Now, this
data is not equal to original raw data.
Following logic is being added to identify the erased
codeword bitflips.
1. Maintain the bitmasks for the codewords which generated
uncorrectable error.
2. Read the raw data again in temp buffer and count the
number of zeros. Since spare bytes are unused in ECC layout and
won’t affect ECC correctability so no need to count number of
zero in spare bytes.
3. If the number of zero is below ECC correctability then it
can be treated as erased CW. In this case, make all the data/oob
of actual user buffers as 0xff.
Change-Id: I5a80cd371a926efa36c40b4db68e78ed78c30536
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following are the major issues in current implementation
1. The mtd layer expects the driver to return non-negative
integer representing the maximum number of bitflips that were
corrected on any one ecc region. The mtd layer takes care of
returning EUCLEAN based on returned number.
2. The read should return the complete data in case of
EBADMSG so move the EBADMSG check in the main read function.
Change-Id: Iab3a28427e8350e8c99368762373f2cbce918786
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. assign ecc strength in mtd structure which will be used by
mtd layer
2. Initialize bitflip_threshold with 3*4 of ecc strength so
that MTD layer will return EUCLEAN if number of ecc correction
are more than bitflip_threshold.
Change-Id: I81cfe6059375117ced7888b877705919287a7be2
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. Added pci entries in AP160 and AP160_2xx dts
2. The wifi pcie card requires to be powered on from GPIO
pins. This patch also adds the same in AP160 dts file and
enable it during PCIe configuration.
Change-Id: Icd8f5741d5df38d46640c78a7475853e77b873a9
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
This patch fixes the erase timeout issue in emmc.
Change-Id: I35031d834fda4ee7560e84787e18e8bc0a3f28fe
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This command helps to debug the phy issues.
Change-Id: If8354d6826795d9ef9d44112582d3b911963bda5
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This patch fixes the issues in below i2c commands.
i2c probe , i2c md and i2c mw commands.
Change-Id: I3dd99e8846452b20a71b0664d325b309f3564579
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This patch enables SPI-NAND support for DK and making
chip select gpio configurable from DTS.
Change-Id: I2ca7d3021fa27da1d83e2a787a1dc626919124f8
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Enabling spi dma driver for ipq40xx. This patch
also enables rx and tx pipe configurable from dts.
Change-Id: Id6009f6e9863ab2cdf8b105461d62aa68e3d004b
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Enable the PPE tx_mac only if the phy link is up else disble
the PPE tx_mac.
Change-Id: I7226a104fa287f8378b98923a00d0caa3f91079d
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This is a snapshot of the spi_nand as of uboot-1.0
commit:
e6434d80905a219860c8ede78377221ded2510f2 (ipq40xx:
Add bit-flip threshold for QPIC NAND)
Change-Id: I91db5822cc450e9d7eb52fca9eab213784547206
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
1. This driver is directly being registered with MTD
layer.So for OOB operations, the device OOB size will be
passed. NAND controller can’t handle the complete OOB so
calculate NAND Controller supported OOB size and overwrite
the device OOB size with that.
2. Enabling 8 bit ECC support in dev0_ecc_cfg register
Change-Id: I5f4297932eea6bed47182d235d081cbe30d1b85c
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
using nand command will change the default nand device to 1. This will
try to read the nor patitions so one if user tries to read the nand partitions.
Change-Id: Id73e89f479b5735fd5b28a871680190f48a76f0e
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
