Now we are adding preamble value to read SBL header if ubi section
is present in the image. But in case of NOR+NAND images, though we are
having SBL in NOR and ubi section is also present and NAND_PREAMBLE
is getting added. which is breaking NOR+NAND sysupgrade.
Added functionality to compare first 12 bytes of section with pre
defined PREAMBLE value. If values matches, add the NAND_PREAMBLE to
read SBL header.
Change-Id: I704ee86cc50aa3ce3b2ab6ec34beab866ffde4b9
Signed-off-by: Anto Norbert <norbrt@codeaurora.org>
This change adds the correct Sbl_Hdr instead of Mbn_Hdr, since
sbl header is different than normal Mbn_Hdr, and adds the sbl
header size as 80.
SBL in nand starts with preamble before the sbl header, so here
it adds the preamble for header start address as well as
src, sig and cert offset values.
Change-Id: I9a56d7b4a51890b74a5ee5fe3047a38801d23803
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Adding device tree support for HK07 in u-boot-2016.
Change-Id: Ib1ea4ffe1df241d2c2cbd3fac4fff3f157eae077
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
To save space in NOR flash, environment loading from flash is
handled differently for NOR and NAND. The size for NOR flash
environment is taken from partition size itself.
Change-Id: I588471b679fad0e96b836d43dc1a0136c5400fc1
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
SPI flash is disabled in DK07-C2, C3 boards. If the
controller tries to probe spi flash, it will wait
indefinitely for response from slave and the
board hangs.
Hence added a maximum timeout of 2 seconds instead
of waiting on a infinte loop for the BAM interrupt
to trigger.
Change-Id: Iabb88352d87e2db756c557e424d64a40c7780310
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Sasirekaa Madhesu <smadhesu@codeaurora.org>
dcache is enabled only during boot from flash.
During JTAG recovery, dcache_enable is skipped
to avoid cache issues in recovery environment.
Change-Id: Ie3003f67c787cbc6b88dc42017aeb2a9508d2ff9
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This patch makes mmc driver dcache aware to keep
the mmc functionality intact, with or without dcache
is enabled.
flush_cache used here does both clean and invalidate
cache thus preventing data loss during unaligned access,
if any.
Change-Id: I0910bd17678d3855bba27e9f8f7c08606774b28d
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This patch adds the support on nand driver to work
when dcache is on.
flush_dcache_range will do both clean and invalidate.
To avoid any data loss when an un-aligned buffer used
in RX path, before giving buffer to bam and after bam
updates the data in buffer, buffer will be flushed.
Change-Id: Ib38d68726efe1692ae94c2be1af61cf29d1c2e50
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Disabling dcache before scheduling secondary cores
and enabling it back after the cores are down.
Change-Id: I73011db903a0da1113d09fb8306b8d3f940ece60
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
In case of 11ad dock (AK01), 8033 phy needs to be reset,
before switch initialization. GPIO32 is configured to
reset phy.
Change-Id: I18a7f05b57c9a02adb27d58d8b4098d44edb49bd
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Some of the newer nand parts can have bit flips in an erased
page due to the process technology used. In this case, ipq
nand controller is not able to identify that page as an erased
page. In case of bitflips, the ECC engine tries to correct the
data and then it generates the uncorrectable error. Now, this
data is not equal to original raw data.
Following logic is being added to identify the erased
codeword bitflips.
1. Maintain the bitmasks for the codewords which generated
uncorrectable error.
2. Read the raw data again in temp buffer and count the
number of zeros. Since spare bytes are unused in ECC layout and
won’t affect ECC correctability so no need to count number of
zero in spare bytes.
3. If the number of zero is below ECC correctability then it
can be treated as erased CW. In this case, make all the data/oob
of actual user buffers as 0xff.
Change-Id: I5a80cd371a926efa36c40b4db68e78ed78c30536
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following are the major issues in current implementation
1. The mtd layer expects the driver to return non-negative
integer representing the maximum number of bitflips that were
corrected on any one ecc region. The mtd layer takes care of
returning EUCLEAN based on returned number.
2. The read should return the complete data in case of
EBADMSG so move the EBADMSG check in the main read function.
Change-Id: Iab3a28427e8350e8c99368762373f2cbce918786
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. assign ecc strength in mtd structure which will be used by
mtd layer
2. Initialize bitflip_threshold with 3*4 of ecc strength so
that MTD layer will return EUCLEAN if number of ecc correction
are more than bitflip_threshold.
Change-Id: I81cfe6059375117ced7888b877705919287a7be2
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
