From e3b2150af9c567c1b07f47ddeb4f413134bb8dfd Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Wed, 19 Oct 2022 07:20:49 +0530 Subject: [PATCH] board: arm: ipq5332: update ethernet clock config Change-Id: I3354354c7cffcb3107293efc54834c5d87556518 Signed-off-by: Vandhiadevan Karunamoorthy --- arch/arm/include/asm/arch-ipq5332/clk.h | 43 +++++- board/qca/arm/ipq5332/clock.c | 174 +++++++++++++----------- 2 files changed, 138 insertions(+), 79 deletions(-) diff --git a/arch/arm/include/asm/arch-ipq5332/clk.h b/arch/arm/include/asm/arch-ipq5332/clk.h index 69b1972992..c0b349d806 100644 --- a/arch/arm/include/asm/arch-ipq5332/clk.h +++ b/arch/arm/include/asm/arch-ipq5332/clk.h @@ -104,8 +104,49 @@ /* * Ethernet Clocks */ +#define GCC_QDSS_AT_CMD_RCGR 0x0182D004 +#define GCC_QDSS_AT_CFG_RCGR 0x0182D008 +#define QDSS_AT_SRC_SEL 1 << 8 +#define QDSS_AT_DIV_SEL 9 << 8 + +#define GCC_PCNOC_BFDCD_CFG_RCGR 0x1831008 +#define GCC_PCNOC_BFDCD_CMD_RCGR 0x1831004 +#define PCCNOC_BFDCD_SRC_SEL 1 << 8 +#define PCCNOC_BFDCD_DIV_SEL 0xF << 0 + +#define GCC_SYSTEM_NOC_BFDCD_CFG_RCGR 0x182E008 +#define GCC_SYSTEM_NOC_BFDCD_CMD_RCGR 0x182E004 +#define SYSTEM_NOC_BFDCD_SRC_SEL 2 << 8 +#define SYSTEM_NOC_BFDCD_DIV_SEL 8 << 0 + +#define NSS_CC_PPE_CMD_RCGR 0x39B003E8 +#define NSS_CC_PPE_CFG_RCGR 0x39B003EC +#define NSS_CC_PPE_SRC_SEL 0x6 << 8 +#define NSS_CC_PPE_DIV_SEL 1 << 0 + +#define GCC_IM_SLEEP_CBCR 0x1834020 +#define NSS_CC_NSS_CSR_CBCR 0x39B005E8 +#define NSS_CC_NSSNOC_NSS_CSR_CBCR 0x39B005EC +#define GCC_UNIPHY0_SYS_CBCR 0x181600C +#define GCC_UNIPHY1_SYS_CBCR 0x1816018 +#define GCC_UNIPHY1_AHB_CBCR 0x181601C +#define GCC_UNIPHY0_AHB_CBCR 0x1816010 +#define NSS_CC_NSSNOC_PPE_CBCR 0x39B00420 +#define GCC_MDIO_SLAVE_AHB_CBCR 0x181200C +#define GCC_MDIO_MASTER_AHB_CBCR 0x1812004 +#define GCC_NSSCC_CBCR 0x1817034 +#define GCC_NSSNOC_NSSCC_CBCR 0x1817030 + +#define PLL_POWER_ON_AND_RESET 0x9B780 +#define PLL_REFERENCE_CLOCK 0x9B784 +#define FREQUENCY_MASK 0xfffffdf0 +#define INTERNAL_48MHZ_CLOCK 0x7 + +#define NSS_CC_CFG_CMD_RCGR 0x39B005E0 +#define NSS_CC_CFG_CFG_RCGR 0x39B005E4 +#define NSS_CC_SRC_SEL 2 << 8 +#define NSS_CC_DIV_SEL 0xF << 0 -#define GCC_UNIPHY_SYS_ADDR 0x0181600C #define GCC_NSSNOC_ATB_CLK 0x01817014 #define GCC_NSSNOC_QOSGEN_REF_CLK 0x0181701C #define GCC_NSSNOC_TIMEOUT_REF_CLK 0x01817020 diff --git a/board/qca/arm/ipq5332/clock.c b/board/qca/arm/ipq5332/clock.c index 65f99593bd..6914634014 100644 --- a/board/qca/arm/ipq5332/clock.c +++ b/board/qca/arm/ipq5332/clock.c @@ -332,90 +332,71 @@ void usb_clock_deinit(void) #endif #ifdef CONFIG_IPQ5332_EDMA -void nssnoc_init(void){ - unsigned int gcc_qdss_at_cmd_rcgr_addr = 0x182D004; - - writel(0x109, gcc_qdss_at_cmd_rcgr_addr + 4); - writel(0x1, gcc_qdss_at_cmd_rcgr_addr); - - /* Enable required NSSNOC clocks */ - writel(readl(GCC_NSSCFG_CLK) | GCC_CBCR_CLK_ENABLE, GCC_NSSCFG_CLK); - - writel(readl(GCC_NSSNOC_ATB_CLK) | GCC_CBCR_CLK_ENABLE, - GCC_NSSNOC_ATB_CLK); - - writel(readl(GCC_NSSNOC_QOSGEN_REF_CLK) | GCC_CBCR_CLK_ENABLE, - GCC_NSSNOC_QOSGEN_REF_CLK); - - writel(readl(GCC_NSSNOC_TIMEOUT_REF_CLK) | GCC_CBCR_CLK_ENABLE, - GCC_NSSNOC_TIMEOUT_REF_CLK); -} - void frequency_init(void) { - unsigned int nss_cc_cfg_addr; - unsigned int gcc_uniphy_sys_addr; - unsigned int gcc_pcnoc_addr; - unsigned int gcc_sysnoc_addr; unsigned int reg_val; /* GCC NSS frequency 100M */ - nss_cc_cfg_addr = 0x39B005E0; - reg_val = readl(nss_cc_cfg_addr + 4); + reg_val = readl(NSS_CC_CFG_CFG_RCGR); reg_val &= ~0x7ff; - writel(reg_val | 0x20f, nss_cc_cfg_addr + 4); + writel(reg_val | NSS_CC_SRC_SEL | NSS_CC_DIV_SEL , + NSS_CC_CFG_CFG_RCGR); - reg_val = readl(nss_cc_cfg_addr); - writel(reg_val | 0x1, nss_cc_cfg_addr); + reg_val = readl(NSS_CC_CFG_CMD_RCGR); + writel(reg_val | CMD_UPDATE, NSS_CC_CFG_CMD_RCGR); + mdelay(1); + writel(reg_val | ROOT_EN, NSS_CC_CFG_CMD_RCGR); - /* GCC CC PPE frequency 353M */ - reg_val = readl(NSS_CC_PPE_FREQUENCY_RCGR + 4); + /* PCNOC_BFDCD frequency for Uniphy AHB 100M */ + reg_val = readl(GCC_PCNOC_BFDCD_CFG_RCGR); reg_val &= ~0x7ff; - writel(reg_val | 0x101, NSS_CC_PPE_FREQUENCY_RCGR + 4); + writel(reg_val | PCCNOC_BFDCD_SRC_SEL | PCCNOC_BFDCD_DIV_SEL, + GCC_PCNOC_BFDCD_CFG_RCGR); + reg_val = readl(GCC_PCNOC_BFDCD_CMD_RCGR); + writel(reg_val | CMD_UPDATE, GCC_PCNOC_BFDCD_CMD_RCGR); + mdelay(1); + writel(reg_val | ROOT_EN, GCC_PCNOC_BFDCD_CMD_RCGR); - reg_val = readl(NSS_CC_PPE_FREQUENCY_RCGR); - writel(reg_val | 0x1, NSS_CC_PPE_FREQUENCY_RCGR); - - /* Uniphy SYS 24M */ - gcc_uniphy_sys_addr = 0x1816004; - reg_val = readl(gcc_uniphy_sys_addr + 4); + /* SYSNOC frequency 266.666667M */ + reg_val = readl(GCC_SYSTEM_NOC_BFDCD_CFG_RCGR); reg_val &= ~0x7ff; - writel(reg_val | 0x1, gcc_uniphy_sys_addr + 4); - /* Update Config */ - reg_val = readl(gcc_uniphy_sys_addr); - writel(reg_val | 0x1, gcc_uniphy_sys_addr); + writel(reg_val | SYSTEM_NOC_BFDCD_SRC_SEL | SYSTEM_NOC_BFDCD_DIV_SEL, + GCC_SYSTEM_NOC_BFDCD_CFG_RCGR); - /* PCNOC frequency for Uniphy AHB 100M */ - gcc_pcnoc_addr = 0x1831004; - reg_val = readl(gcc_pcnoc_addr + 4); - reg_val &= ~0x7ff; - writel(reg_val | 0x10F, gcc_pcnoc_addr + 4); - /* Update Config */ - reg_val = readl(gcc_pcnoc_addr); - writel(reg_val | 0x1, gcc_pcnoc_addr); + reg_val = readl(GCC_SYSTEM_NOC_BFDCD_CMD_RCGR); + writel(reg_val | CMD_UPDATE, GCC_SYSTEM_NOC_BFDCD_CMD_RCGR); + mdelay(1); + writel(reg_val | ROOT_EN, GCC_SYSTEM_NOC_BFDCD_CMD_RCGR); - /* SYSNOC frequency 343M */ - gcc_sysnoc_addr = 0x182E004; - reg_val = readl(gcc_sysnoc_addr + 4); + /* Port Clock rate 200M */ + reg_val = readl(NSS_CC_PPE_CFG_RCGR); reg_val &= ~0x7ff; - writel(reg_val | 0x206, gcc_sysnoc_addr + 4); - /* Update Config */ - reg_val = readl(gcc_sysnoc_addr); - writel(reg_val | 0x1, gcc_sysnoc_addr); + writel(reg_val | NSS_CC_PPE_SRC_SEL | NSS_CC_PPE_DIV_SEL, + NSS_CC_PPE_CFG_RCGR); + + reg_val = readl( NSS_CC_PPE_CMD_RCGR); + writel(reg_val | CMD_UPDATE, NSS_CC_PPE_CMD_RCGR); + mdelay(1); + writel(reg_val | ROOT_EN, NSS_CC_PPE_CMD_RCGR); + + reg_val = readl(GCC_NSSCC_CBCR); + writel(reg_val | CLK_ENABLE, GCC_NSSCC_CBCR); + + reg_val = readl(GCC_NSSNOC_NSSCC_CBCR); + writel(reg_val | CLK_ENABLE, GCC_NSSNOC_NSSCC_CBCR); + } void fixed_nss_csr_clock_init(void) { - unsigned int gcc_nss_csr_addr; unsigned int reg_val; /* NSS CSR and NSSNOC CSR Clock init */ - gcc_nss_csr_addr = 0x39B005E8; - reg_val = readl(gcc_nss_csr_addr); - writel(reg_val | GCC_CBCR_CLK_ENABLE, gcc_nss_csr_addr); - /* NSSNOC CSR */ - reg_val = readl(gcc_nss_csr_addr + 0x4); - writel(reg_val | GCC_CBCR_CLK_ENABLE, gcc_nss_csr_addr + 0x4); + reg_val = readl(NSS_CC_NSSNOC_NSS_CSR_CBCR); + writel(reg_val | CLK_ENABLE, NSS_CC_NSSNOC_NSS_CSR_CBCR); + + reg_val = readl(NSS_CC_NSS_CSR_CBCR); + writel(reg_val | CLK_ENABLE, NSS_CC_NSS_CSR_CBCR); } void fixed_sys_clock_init(void) @@ -424,6 +405,10 @@ void fixed_sys_clock_init(void) /* SYS Clock init */ /* Enable AHB and SYS clk of CMN */ + + reg_val = readl(GCC_IM_SLEEP_CBCR); + writel(reg_val | CLK_ENABLE, GCC_IM_SLEEP_CBCR); + reg_val = readl(GCC_CMN_BLK_ADDR + GCC_CMN_BLK_AHB_CBCR_OFFSET); writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_CMN_BLK_ADDR + GCC_CMN_BLK_AHB_CBCR_OFFSET); @@ -435,19 +420,20 @@ void fixed_sys_clock_init(void) void fixed_uniphy_clock_init(void) { - int i; unsigned int reg_val; /* Uniphy AHB AND SYS CBCR init */ - for (i = 0; i < 2; i++) { - reg_val = readl(GCC_UNIPHY_SYS_ADDR + i*0x10); - writel(reg_val | GCC_CBCR_CLK_ENABLE, - GCC_UNIPHY_SYS_ADDR + i*0x10); + reg_val = readl(GCC_UNIPHY0_SYS_CBCR); + writel(reg_val | CLK_ENABLE, GCC_UNIPHY0_SYS_CBCR); - reg_val = readl((GCC_UNIPHY_SYS_ADDR + 0x4) + i*0x10); - writel(reg_val | GCC_CBCR_CLK_ENABLE, - (GCC_UNIPHY_SYS_ADDR + 0x4) + i*0x10); - } + reg_val = readl(GCC_UNIPHY1_SYS_CBCR); + writel(reg_val | CLK_ENABLE, GCC_UNIPHY1_SYS_CBCR); + + reg_val = readl(GCC_UNIPHY0_AHB_CBCR); + writel(reg_val | CLK_ENABLE, GCC_UNIPHY0_AHB_CBCR); + + reg_val = readl(GCC_UNIPHY1_AHB_CBCR); + writel(reg_val | CLK_ENABLE, GCC_UNIPHY1_AHB_CBCR); } void port_mac_clock_init(void) @@ -458,7 +444,8 @@ void port_mac_clock_init(void) /* Port Mac Clock init */ for (i = 0; i < 2; i++) { reg_val = readl(GCC_PORT_MAC_ADDR + i*0x8); - writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_PORT_MAC_ADDR + i*0x8); + writel(reg_val | GCC_CBCR_CLK_ENABLE, + GCC_PORT_MAC_ADDR + i*0x8); } } @@ -499,6 +486,16 @@ void cfg_clock_init(void) writel(reg_val | GCC_CBCR_CLK_ENABLE, NSS_CC_PPE_SWITCH_BTQ_ADDR); } +void mdio_clock_init(void) +{ + unsigned int reg_val; + + /* MDIO Master Clock init */ + reg_val = readl(GCC_MDIO_MASTER_AHB_CBCR); + writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_MDIO_MASTER_AHB_CBCR); +} + + void noc_clock_init(void) { unsigned int reg_val; @@ -509,9 +506,6 @@ void noc_clock_init(void) reg_val = readl(GCC_NSSNOC_SNOC_1_CBCR); writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_NSSNOC_SNOC_1_CBCR); - - reg_val = readl(GCC_MEM_NOC_SNOC_AXI_CBCR); - writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_MEM_NOC_SNOC_AXI_CBCR); } void uniphy_clock_enable(enum uniphy_clk_type clk_type, bool enable) @@ -557,15 +551,39 @@ void fixed_clock_init(void) cfg_clock_init(); + mdio_clock_init(); + noc_clock_init(); } +void cmbblk_init(void) +{ +#ifndef CONFIG_IPQ5332_RUMI + unsigned int reg_val; + + reg_val = readl(PLL_REFERENCE_CLOCK); + reg_val = (reg_val & FREQUENCY_MASK) | INTERNAL_48MHZ_CLOCK; + writel(reg_val, PLL_REFERENCE_CLOCK); + reg_val = readl(PLL_POWER_ON_AND_RESET); + reg_val = reg_val | 0x40; + writel(reg_val, PLL_POWER_ON_AND_RESET); + mdelay(10); + reg_val = reg_val & (~0x40); + writel(reg_val, PLL_POWER_ON_AND_RESET); + mdelay(10); + writel(0xbf, PLL_POWER_ON_AND_RESET); + mdelay(10); + writel(0xff, PLL_POWER_ON_AND_RESET); + mdelay(10); +#endif +} + void eth_clock_init(void) { - nssnoc_init(); - fixed_clock_init(); uniphy_clk_init(true); + + cmbblk_init(); } #endif