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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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drivers: net: ipq9574: Fix network configurations
This patch updates the following: 1) Updates NSS NOC clock frequencies to expected clock rates 2) Add Debug prints during eth_halt which can help debug issues 3) Update ACL structure and configurations for ipq9574 platform as required 4) Disable the MIB counters reset bit so that those counter registers values can be dumped to check stats 5) Update VSI configurations for cases when BRIDGED_MODE config is disabled 6) Update the VSI configuration to avoid flooding from one LAN port to another Change-Id: I39f20a57c08205fbeb669c93b6459cf8e184098d Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
This commit is contained in:
Selvam Sathappan Periakaruppan
Gerrit - the friendly Code Review server
parent
4291c86117
commit
e0726bab13
4 changed files with 54 additions and 15 deletions
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@ -849,8 +849,16 @@ void set_function_select_as_mdc_mdio(void)
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}
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}
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void nssnoc_init(void)
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{
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void nssnoc_init(void){
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unsigned int gcc_nssnoc_memnoc_bfdcd_cmd_rcgr_addr = 0x1817004;
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unsigned int gcc_qdss_at_cmd_rcgr_addr = 0x182D004;
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writel(0x102, gcc_nssnoc_memnoc_bfdcd_cmd_rcgr_addr + 4);
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writel(0x3, gcc_nssnoc_memnoc_bfdcd_cmd_rcgr_addr);
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writel(0x109, gcc_qdss_at_cmd_rcgr_addr + 4);
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writel(0x3, gcc_qdss_at_cmd_rcgr_addr);
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/* Enable required NSSNOC clocks */
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writel(readl(GCC_MEM_NOC_NSSNOC_CLK) | GCC_CBCR_CLK_ENABLE,
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GCC_MEM_NOC_NSSNOC_CLK);
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@ -1305,6 +1305,37 @@ static int ipq9574_edma_wr_macaddr(struct eth_device *dev)
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static void ipq9574_eth_halt(struct eth_device *dev)
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{
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pr_debug("\n\n*****GMAC0 info*****\n");
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pr_debug("GMAC0 RXPAUSE(0x3a001044):%x\n", readl(0x3a001044));
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pr_debug("GMAC0 TXPAUSE(0x3a0010A4):%x\n", readl(0x3a0010A4));
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pr_debug("GMAC0 RXGOODBYTE_L(0x3a001084):%x\n", readl(0x3a001084));
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pr_debug("GMAC0 RXGOODBYTE_H(0x3a001088):%x\n", readl(0x3a001088));
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pr_debug("GMAC0 RXBADBYTE_L(0x3a00108c):%x\n", readl(0x3a00108c));
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pr_debug("GMAC0 RXBADBYTE_H(0x3a001090):%x\n", readl(0x3a001090));
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pr_debug("\n\n*****GMAC1 info*****\n");
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pr_debug("GMAC1 RXPAUSE(0x3a001244):%x\n", readl(0x3a001244));
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pr_debug("GMAC1 TXPAUSE(0x3a0012A4):%x\n", readl(0x3a0012A4));
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pr_debug("GMAC1 RXGOODBYTE_L(0x3a001284):%x\n", readl(0x3a001284));
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pr_debug("GMAC1 RXGOODBYTE_H(0x3a001288):%x\n", readl(0x3a001288));
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pr_debug("GMAC1 RXBADBYTE_L(0x3a00128c):%x\n", readl(0x3a00128c));
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pr_debug("GMAC1 RXBADBYTE_H(0x3a001290):%x\n", readl(0x3a001290));
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pr_debug("\n\n*****GMAC2 info*****\n");
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pr_debug("GMAC2 RXPAUSE(0x3a001444):%x\n", readl(0x3a001444));
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pr_debug("GMAC2 TXPAUSE(0x3a0014A4):%x\n", readl(0x3a0014A4));
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pr_debug("GMAC2 RXGOODBYTE_L(0x3a001484):%x\n", readl(0x3a001484));
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pr_debug("GMAC2 RXGOODBYTE_H(0x3a001488):%x\n", readl(0x3a001488));
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pr_debug("GMAC2 RXBADBYTE_L(0x3a00148c):%x\n", readl(0x3a00148c));
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pr_debug("GMAC2 RXBADBYTE_H(0x3a001490):%x\n", readl(0x3a001490));
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pr_debug("\n\n*****GMAC3 info*****\n");
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pr_debug("GMAC3 RXPAUSE(0x3a001644):%x\n", readl(0x3a001644));
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pr_debug("GMAC3 TXPAUSE(0x3a0016A4):%x\n", readl(0x3a0016A4));
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pr_debug("GMAC3 RXGOODBYTE_L(0x3a001684):%x\n", readl(0x3a001684));
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pr_debug("GMAC3 RXGOODBYTE_H(0x3a001688):%x\n", readl(0x3a001688));
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pr_debug("GMAC3 RXBADBYTE_L(0x3a00168c):%x\n", readl(0x3a00168c));
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pr_debug("GMAC3 RXBADBYTE_H(0x3a001690):%x\n", readl(0x3a001690));
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pr_info("%s: done\n", __func__);
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}
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@ -110,8 +110,8 @@ void ipq9574_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_n
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hw_reg.bf.pri = 0x0;
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}
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hw_reg.bf.src_0 = 0x6;
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hw_reg.bf.src_1 = 0x7;
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hw_reg.bf.src_0 = 0x0;
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hw_reg.bf.src_1 = 0x3f;
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ppe_ipo_rule_reg_set(&hw_reg, rule_id);
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ppe_ipo_mask_reg_set(&hw_mask, rule_id);
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ppe_ipo_action_set(&hw_act, rule_id);
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@ -153,7 +153,7 @@ static void ipq9574_ppe_ucast_queue_map_tbl_queue_id_set(int queue, int port)
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*/
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static void ipq9574_vsi_setup(int vsi, uint8_t group_mask)
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{
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uint32_t val = (group_mask << 24 | group_mask << 16 | group_mask << 8
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uint32_t val = (group_mask << 24 | group_mask << 16 | 0x1
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| group_mask);
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/* Set mask */
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@ -473,7 +473,7 @@ void ipq9574_pqsgmii_speed_set(int port, int speed, int status)
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ppe_port_bridge_txmac_set(port + 1, status);
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ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_SPEED + (0x200 * port), speed);
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ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_ENABLE + (0x200 * port), 0x73);
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ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x5);
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ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x1);
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}
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/*
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@ -895,6 +895,8 @@ void ipq9574_ppe_provision_init(void)
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ipq9574_ppe_vp_port_tbl_set(2, 3);
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ipq9574_ppe_vp_port_tbl_set(3, 4);
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ipq9574_ppe_vp_port_tbl_set(4, 5);
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ipq9574_ppe_vp_port_tbl_set(5, 6);
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ipq9574_ppe_vp_port_tbl_set(6, 7);
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#endif
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/* Unicast priority map */
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@ -914,10 +916,6 @@ void ipq9574_ppe_provision_init(void)
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ipq9574_ppe_e_sp_cfg_tbl_drr_id_set(i);
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}
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/* sp_cfg_l0 and sp_cfg_l1 configuration */
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ipq9574_ppe_reg_write(IPQ9574_PPE_TM_SHP_CFG_L0, 0x12b);
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ipq9574_ppe_reg_write(IPQ9574_PPE_TM_SHP_CFG_L1, 0x3f);
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/* Port0 multicast queue */
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ipq9574_ppe_reg_write(0x409000, 0x00000000);
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ipq9574_ppe_reg_write(0x403000, 0x00401000);
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@ -956,6 +954,8 @@ void ipq9574_ppe_provision_init(void)
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ipq9574_vsi_setup(3, 0x05);
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ipq9574_vsi_setup(4, 0x09);
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ipq9574_vsi_setup(5, 0x11);
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ipq9574_vsi_setup(6, 0x21);
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ipq9574_vsi_setup(7, 0x41);
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#endif
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/* Port 0-7 STP */
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@ -77,14 +77,14 @@ struct ipo_rule_reg {
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uint32_t fake_mac_header:1;
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uint32_t range_en:1;
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uint32_t inverse_en:1;
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uint32_t rule_type:4;
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uint32_t src_type:2;
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uint32_t src_0:3;
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uint32_t src_1:5;
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uint32_t rule_type:5;
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uint32_t src_type:3;
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uint32_t src_0:1;
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uint32_t src_1:7;
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uint32_t pri:9;
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uint32_t res_chain:1;
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uint32_t post_routing_en:1;
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uint32_t _reserved0:16;
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uint32_t _reserved0:14;
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};
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union ipo_rule_reg_u {
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