diff --git a/board/qca/arm/ipq9574/ipq9574.c b/board/qca/arm/ipq9574/ipq9574.c index 8439af636e..c06d3602aa 100644 --- a/board/qca/arm/ipq9574/ipq9574.c +++ b/board/qca/arm/ipq9574/ipq9574.c @@ -849,8 +849,16 @@ void set_function_select_as_mdc_mdio(void) } } -void nssnoc_init(void) -{ +void nssnoc_init(void){ + unsigned int gcc_nssnoc_memnoc_bfdcd_cmd_rcgr_addr = 0x1817004; + unsigned int gcc_qdss_at_cmd_rcgr_addr = 0x182D004; + + writel(0x102, gcc_nssnoc_memnoc_bfdcd_cmd_rcgr_addr + 4); + writel(0x3, gcc_nssnoc_memnoc_bfdcd_cmd_rcgr_addr); + + writel(0x109, gcc_qdss_at_cmd_rcgr_addr + 4); + writel(0x3, gcc_qdss_at_cmd_rcgr_addr); + /* Enable required NSSNOC clocks */ writel(readl(GCC_MEM_NOC_NSSNOC_CLK) | GCC_CBCR_CLK_ENABLE, GCC_MEM_NOC_NSSNOC_CLK); diff --git a/drivers/net/ipq9574/ipq9574_edma.c b/drivers/net/ipq9574/ipq9574_edma.c index b66d80024b..c3109438e6 100644 --- a/drivers/net/ipq9574/ipq9574_edma.c +++ b/drivers/net/ipq9574/ipq9574_edma.c @@ -1305,6 +1305,37 @@ static int ipq9574_edma_wr_macaddr(struct eth_device *dev) static void ipq9574_eth_halt(struct eth_device *dev) { + pr_debug("\n\n*****GMAC0 info*****\n"); + pr_debug("GMAC0 RXPAUSE(0x3a001044):%x\n", readl(0x3a001044)); + pr_debug("GMAC0 TXPAUSE(0x3a0010A4):%x\n", readl(0x3a0010A4)); + pr_debug("GMAC0 RXGOODBYTE_L(0x3a001084):%x\n", readl(0x3a001084)); + pr_debug("GMAC0 RXGOODBYTE_H(0x3a001088):%x\n", readl(0x3a001088)); + pr_debug("GMAC0 RXBADBYTE_L(0x3a00108c):%x\n", readl(0x3a00108c)); + pr_debug("GMAC0 RXBADBYTE_H(0x3a001090):%x\n", readl(0x3a001090)); + + pr_debug("\n\n*****GMAC1 info*****\n"); + pr_debug("GMAC1 RXPAUSE(0x3a001244):%x\n", readl(0x3a001244)); + pr_debug("GMAC1 TXPAUSE(0x3a0012A4):%x\n", readl(0x3a0012A4)); + pr_debug("GMAC1 RXGOODBYTE_L(0x3a001284):%x\n", readl(0x3a001284)); + pr_debug("GMAC1 RXGOODBYTE_H(0x3a001288):%x\n", readl(0x3a001288)); + pr_debug("GMAC1 RXBADBYTE_L(0x3a00128c):%x\n", readl(0x3a00128c)); + pr_debug("GMAC1 RXBADBYTE_H(0x3a001290):%x\n", readl(0x3a001290)); + + pr_debug("\n\n*****GMAC2 info*****\n"); + pr_debug("GMAC2 RXPAUSE(0x3a001444):%x\n", readl(0x3a001444)); + pr_debug("GMAC2 TXPAUSE(0x3a0014A4):%x\n", readl(0x3a0014A4)); + pr_debug("GMAC2 RXGOODBYTE_L(0x3a001484):%x\n", readl(0x3a001484)); + pr_debug("GMAC2 RXGOODBYTE_H(0x3a001488):%x\n", readl(0x3a001488)); + pr_debug("GMAC2 RXBADBYTE_L(0x3a00148c):%x\n", readl(0x3a00148c)); + pr_debug("GMAC2 RXBADBYTE_H(0x3a001490):%x\n", readl(0x3a001490)); + + pr_debug("\n\n*****GMAC3 info*****\n"); + pr_debug("GMAC3 RXPAUSE(0x3a001644):%x\n", readl(0x3a001644)); + pr_debug("GMAC3 TXPAUSE(0x3a0016A4):%x\n", readl(0x3a0016A4)); + pr_debug("GMAC3 RXGOODBYTE_L(0x3a001684):%x\n", readl(0x3a001684)); + pr_debug("GMAC3 RXGOODBYTE_H(0x3a001688):%x\n", readl(0x3a001688)); + pr_debug("GMAC3 RXBADBYTE_L(0x3a00168c):%x\n", readl(0x3a00168c)); + pr_debug("GMAC3 RXBADBYTE_H(0x3a001690):%x\n", readl(0x3a001690)); pr_info("%s: done\n", __func__); } diff --git a/drivers/net/ipq9574/ipq9574_ppe.c b/drivers/net/ipq9574/ipq9574_ppe.c index 30d3eddaf6..5b7be0e14c 100644 --- a/drivers/net/ipq9574/ipq9574_ppe.c +++ b/drivers/net/ipq9574/ipq9574_ppe.c @@ -110,8 +110,8 @@ void ipq9574_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_n hw_reg.bf.pri = 0x0; } - hw_reg.bf.src_0 = 0x6; - hw_reg.bf.src_1 = 0x7; + hw_reg.bf.src_0 = 0x0; + hw_reg.bf.src_1 = 0x3f; ppe_ipo_rule_reg_set(&hw_reg, rule_id); ppe_ipo_mask_reg_set(&hw_mask, rule_id); ppe_ipo_action_set(&hw_act, rule_id); @@ -153,7 +153,7 @@ static void ipq9574_ppe_ucast_queue_map_tbl_queue_id_set(int queue, int port) */ static void ipq9574_vsi_setup(int vsi, uint8_t group_mask) { - uint32_t val = (group_mask << 24 | group_mask << 16 | group_mask << 8 + uint32_t val = (group_mask << 24 | group_mask << 16 | 0x1 | group_mask); /* Set mask */ @@ -473,7 +473,7 @@ void ipq9574_pqsgmii_speed_set(int port, int speed, int status) ppe_port_bridge_txmac_set(port + 1, status); ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_SPEED + (0x200 * port), speed); ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_ENABLE + (0x200 * port), 0x73); - ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x5); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x1); } /* @@ -895,6 +895,8 @@ void ipq9574_ppe_provision_init(void) ipq9574_ppe_vp_port_tbl_set(2, 3); ipq9574_ppe_vp_port_tbl_set(3, 4); ipq9574_ppe_vp_port_tbl_set(4, 5); + ipq9574_ppe_vp_port_tbl_set(5, 6); + ipq9574_ppe_vp_port_tbl_set(6, 7); #endif /* Unicast priority map */ @@ -914,10 +916,6 @@ void ipq9574_ppe_provision_init(void) ipq9574_ppe_e_sp_cfg_tbl_drr_id_set(i); } - /* sp_cfg_l0 and sp_cfg_l1 configuration */ - ipq9574_ppe_reg_write(IPQ9574_PPE_TM_SHP_CFG_L0, 0x12b); - ipq9574_ppe_reg_write(IPQ9574_PPE_TM_SHP_CFG_L1, 0x3f); - /* Port0 multicast queue */ ipq9574_ppe_reg_write(0x409000, 0x00000000); ipq9574_ppe_reg_write(0x403000, 0x00401000); @@ -956,6 +954,8 @@ void ipq9574_ppe_provision_init(void) ipq9574_vsi_setup(3, 0x05); ipq9574_vsi_setup(4, 0x09); ipq9574_vsi_setup(5, 0x11); + ipq9574_vsi_setup(6, 0x21); + ipq9574_vsi_setup(7, 0x41); #endif /* Port 0-7 STP */ diff --git a/drivers/net/ipq9574/ipq9574_ppe.h b/drivers/net/ipq9574/ipq9574_ppe.h index c1ec72dc45..9e0a8d953e 100644 --- a/drivers/net/ipq9574/ipq9574_ppe.h +++ b/drivers/net/ipq9574/ipq9574_ppe.h @@ -77,14 +77,14 @@ struct ipo_rule_reg { uint32_t fake_mac_header:1; uint32_t range_en:1; uint32_t inverse_en:1; - uint32_t rule_type:4; - uint32_t src_type:2; - uint32_t src_0:3; - uint32_t src_1:5; + uint32_t rule_type:5; + uint32_t src_type:3; + uint32_t src_0:1; + uint32_t src_1:7; uint32_t pri:9; uint32_t res_chain:1; uint32_t post_routing_en:1; - uint32_t _reserved0:16; + uint32_t _reserved0:14; }; union ipo_rule_reg_u {