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board: qca: arm: ipq5332: Enable GCC_PCIE3X1_PHY_AHB_CBCR clock

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The pcie0 and usb uses combo phy, for usb 3.0 GCC_PCIE3X1_PHY_AHB_CBCR
clock has to be enabled

Change-Id: I281773f40bf7d32b27a27e7dc5e5d531ae3a3dc0
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This commit is contained in:
Timple Raj M 2023-05-10 15:45:12 +05:30 • committed by Gerrit - the friendly Code Review server
parent 75c182c3ec
commit d94f0f3931
1 changed files with 1 additions and 0 deletions
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board/qca/arm/ipq5332/ipq5332.c
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@ -754,6 +754,7 @@ static void usb_init_hsphy(void __iomem *phybase, int ssphy)
static void usb_init_ssphy(void __iomem *phybase)
{
writel(CLK_ENABLE, GCC_PCIE3X1_PHY_AHB_CBCR);
writel(CLK_ENABLE, GCC_USB0_PHY_CFG_AHB_CBCR);
writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR);
udelay(100);