From d94f0f39313b3f7ec3f58dc595aceed37790e078 Mon Sep 17 00:00:00 2001 From: Timple Raj M Date: Wed, 10 May 2023 15:45:12 +0530 Subject: [PATCH] board: qca: arm: ipq5332: Enable GCC_PCIE3X1_PHY_AHB_CBCR clock The pcie0 and usb uses combo phy, for usb 3.0 GCC_PCIE3X1_PHY_AHB_CBCR clock has to be enabled Change-Id: I281773f40bf7d32b27a27e7dc5e5d531ae3a3dc0 Signed-off-by: Timple Raj M --- board/qca/arm/ipq5332/ipq5332.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/qca/arm/ipq5332/ipq5332.c b/board/qca/arm/ipq5332/ipq5332.c index e9cb8c758a..df8bb01f1c 100644 --- a/board/qca/arm/ipq5332/ipq5332.c +++ b/board/qca/arm/ipq5332/ipq5332.c @@ -754,6 +754,7 @@ static void usb_init_hsphy(void __iomem *phybase, int ssphy) static void usb_init_ssphy(void __iomem *phybase) { + writel(CLK_ENABLE, GCC_PCIE3X1_PHY_AHB_CBCR); writel(CLK_ENABLE, GCC_USB0_PHY_CFG_AHB_CBCR); writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR); udelay(100);