diff --git a/board/qca/arm/ipq5332/clock.c b/board/qca/arm/ipq5332/clock.c
index c6936bab1a..f08193106c 100644
--- a/board/qca/arm/ipq5332/clock.c
+++ b/board/qca/arm/ipq5332/clock.c
@@ -84,7 +84,6 @@ int uart_clock_config(struct ipq_serial_platdata *plat)
 #ifdef CONFIG_QCA_MMC
 void emmc_clock_init(void)
 {
-#ifdef QCA_CLOCK_ENABLE
 	int cfg;
 
 	/* Configure sdcc1_apps_clk_src */
@@ -111,9 +110,7 @@ void emmc_clock_init(void)
 	udelay(10);
 	writel(readl(GCC_SDCC1_AHB_CBCR) | CLK_ENABLE, GCC_SDCC1_AHB_CBCR);
 	udelay(10);
-#else
 	return;
-#endif
 }
 
 void emmc_clock_reset(void)
@@ -126,7 +123,6 @@ void emmc_clock_reset(void)
 #ifdef CONFIG_PCI_IPQ
 void pcie_v2_clock_init(int pcie_id)
 {
-#ifdef QCA_CLOCK_ENABLE
 	int cfg, cfg1,cfg2;
 	static int clk_configure;
 
@@ -215,14 +211,11 @@ void pcie_v2_clock_init(int pcie_id)
 	writel(CLK_ENABLE, GCC_SNOC_PCIE3_1LANE_S_CBCR);
 	writel(CLK_ENABLE, GCC_SNOC_PCIE3_1LANE_1_M_CBCR);
 	writel(CLK_ENABLE, GCC_SNOC_PCIE3_1LANE_1_S_CBCR);
-#else
 	return;
-#endif
 }
 
 void pcie_v2_clock_deinit(int pcie_id)
 {
-#ifdef QCA_CLOCK_ENABLE
 	writel(0x0, GCC_SNOC_PCIE3_2LANE_M_CBCR);
 	writel(0x0, GCC_SNOC_PCIE3_2LANE_S_CBCR);
 	writel(0x0, GCC_SNOC_PCIE3_1LANE_M_CBCR);
@@ -257,15 +250,12 @@ void pcie_v2_clock_deinit(int pcie_id)
 		writel(0x0, GCC_PCIE3X1_1_AUX_CBCR);
 		break;
 	}
-#else
 	return;
-#endif
 }
 #endif
 #ifdef CONFIG_USB_XHCI_IPQ
 void usb_clock_init(void)
 {
-#ifdef QCA_CLOCK_ENABLE
 	int cfg;
 
 	/* Configure usb0_master_clk_src */
@@ -317,23 +307,18 @@ void usb_clock_init(void)
 	writel(CLK_ENABLE, GCC_USB0_PHY_CFG_AHB_CBCR);
 	writel(CLK_ENABLE, GCC_USB0_AUX_CBCR);
 	writel(CLK_ENABLE, GCC_USB0_LFPS_CBCR);
-#else
 	return;
-#endif
 }
 
 void usb_clock_deinit(void)
 {
-#ifdef QCA_CLOCK_ENABLE
 	writel(0x0, GCC_USB0_PHY_CFG_AHB_CBCR);
 	writel(0x4220, GCC_USB0_MASTER_CBCR);
 	writel(0x0, GCC_USB0_SLEEP_CBCR);
 	writel(0x0, GCC_USB0_MOCK_UTMI_CBCR);
 	writel(0x0, GCC_USB0_AUX_CBCR);
 	writel(0x0, GCC_USB0_LFPS_CBCR);
-#else
 	return;
-#endif
 }
 #endif
 
@@ -566,7 +551,6 @@ void fixed_clock_init(void)
 
 void cmbblk_init(void)
 {
-#ifndef CONFIG_IPQ5332_RUMI
 	unsigned int reg_val;
 
 	reg_val = readl(PLL_REFERENCE_CLOCK);
@@ -582,7 +566,6 @@ void cmbblk_init(void)
 	reg_val |= BIT(6);
 	writel(reg_val, PLL_POWER_ON_AND_RESET);
 	mdelay(10);
-#endif
 }
 
 void eth_clock_init(void)
diff --git a/drivers/net/ipq5332/ipq5332_edma.c b/drivers/net/ipq5332/ipq5332_edma.c
index af49ada2db..95cc882aea 100644
--- a/drivers/net/ipq5332/ipq5332_edma.c
+++ b/drivers/net/ipq5332/ipq5332_edma.c
@@ -57,7 +57,6 @@ phy_info_t *swt_info[QCA8084_MAX_PORTS] = {0};
 ipq5332_edma_port_info_t *port_info[IPQ5332_PHY_MAX] = {0};
 int sgmii_mode[2] = {0};
 
-#ifndef CONFIG_IPQ5332_RUMI
 extern void ipq_phy_addr_fixup(void);
 extern void ipq_clock_init(void);
 extern int ipq_sw_mdio_init(const char *);
@@ -82,15 +81,12 @@ extern int ipq_qca8337_link_update(ipq_s17c_swt_cfg_t *s17c_swt_cfg);
 extern void ipq_s17c_switch_reset(int gpio);
 ipq_s17c_swt_cfg_t s17c_swt_cfg;
 #endif
-#endif
 
 static int tftp_acl_our_port;
-#ifndef CONFIG_IPQ5332_RUMI
 #ifdef CONFIG_QCA8084_SWT_MODE
 static int qca8084_swt_enb = 0;
 static int qca8084_chip_detect = 0;
 #endif
-#endif
 
 /*
  * EDMA hardware instance
@@ -885,7 +881,6 @@ static void ipq5332_edma_disable_intr(struct ipq5332_edma_hw *ehw)
 				IPQ5332_EDMA_MASK_INT_DISABLE);
 }
 
-#ifndef CONFIG_IPQ5332_RUMI
 void print_eth_info(int mac_unit, int phy_id, char *status, int speed,
 				char *duplex)
 {
@@ -893,14 +888,11 @@ void print_eth_info(int mac_unit, int phy_id, char *status, int speed,
 			status, speed, duplex);
 }
 
-#endif
-
 static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
 {
 	int i;
 	u8 status = 0;
 	int mac_speed = 0x1;
-#ifndef CONFIG_IPQ5332_RUMI
 	struct ipq5332_eth_dev *priv = eth_dev->priv;
 	struct phy_ops *phy_get_ops;
 	static fal_port_speed_t old_speed[IPQ5332_PHY_MAX] =
@@ -914,14 +906,12 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
 	int phy_addr = -1, ret = -1;
 	phy_info_t *phy_info;
 	int sgmii_mode = EPORT_WRAPPER_SGMII0_RGMII4, sfp_mode = -1;
-#endif
 	/*
 	 * Check PHY link, speed, Duplex on all phys.
 	 * we will proceed even if single link is up
 	 * else we will return with -1;
 	 */
 	for (i =  0; i < IPQ5332_PHY_MAX; i++) {
-#ifndef CONFIG_IPQ5332_RUMI
 		phy_info = port_info[i]->phy_info;
 		if (phy_info->phy_type == UNUSED_PHY_TYPE)
 			continue;
@@ -999,9 +989,6 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
 					dp[duplex]);
 			continue;
 		}
-#endif
-
-#ifndef CONFIG_IPQ5332_RUMI
 		/*
 		 * Note: If the current port link is up and its speed is
 		 * different from its initially configured speed, only then
@@ -1136,21 +1123,12 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
 		}
 
 		ipq5332_speed_clock_set(i, clk);
-#else
-		ppe_port_bridge_txmac_set(i, 1);
-		//FAL_SPEED_5000
-		mac_speed = 0x5;
-		ipq5332_uxsgmii_speed_set(i, mac_speed,
-						FAL_DUPLEX_BUTT, status);
-#endif
 	}
 
-#ifndef CONFIG_IPQ5332_RUMI
 	if (linkup <= 0) {
 		/* No PHY link is alive */
 		return -1;
 	}
-#endif
 
 	pr_info("%s: done\n", __func__);
 
@@ -1711,7 +1689,6 @@ int ipq5332_edma_init(void *edma_board_cfg)
 	int i;
 	int ret = -1;
 	ipq5332_edma_board_cfg_t ledma_cfg, *edma_cfg;
-#ifndef	CONFIG_IPQ5332_RUMI
 	phy_info_t *phy_info;
 	int phy_id;
 	uint32_t phy_chip_id, phy_chip_id1, phy_chip_id2;
@@ -1726,13 +1703,11 @@ int ipq5332_edma_init(void *edma_board_cfg)
 	int s17c_swt_enb = 0, s17c_rst_gpio = 0;
 #endif
 	int node, phy_addr, mode, phy_node = -1;
-#endif
 	/*
 	 * Init non cache buffer
 	 */
 	noncached_init();
 
-#ifndef CONFIG_IPQ5332_RUMI
 	node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
 #ifdef CONFIG_QCA8084_SWT_MODE
 	qca8084_swt_enb = fdtdec_get_uint(gd->fdt_blob, node,
@@ -1785,7 +1760,6 @@ int ipq5332_edma_init(void *edma_board_cfg)
 		printf("Error:switch_mac_mode0 not specified in dts");
 		return mode;
 	}
-#endif
 
 	memset(c_info, 0, (sizeof(c_info) * IPQ5332_EDMA_DEV));
 	memset(enet_addr, 0, sizeof(enet_addr));
@@ -1862,7 +1836,6 @@ int ipq5332_edma_init(void *edma_board_cfg)
 		ipq5332_edma_dev[i]->c_info = c_info[i];
 		ipq5332_edma_hw_addr = IPQ5332_EDMA_CFG_BASE;
 
-#ifndef CONFIG_IPQ5332_RUMI
 		ret = ipq_sw_mdio_init(edma_cfg->phy_name);
 		if (ret)
 			goto init_failed;
@@ -1979,14 +1952,12 @@ int ipq5332_edma_init(void *edma_board_cfg)
 			break;
 			}
 		}
-#endif
 
 		ret = ipq5332_edma_hw_init(hw[i]);
 
 		if (ret)
 			goto init_failed;
 
-#ifndef CONFIG_IPQ5332_RUMI
 #ifdef CONFIG_QCA8084_SWT_MODE
 		/** QCA8084 switch specific configurations */
 		if (qca8084_swt_enb && qca8084_chip_detect) {
@@ -2020,7 +1991,6 @@ int ipq5332_edma_init(void *edma_board_cfg)
 #ifdef CONFIG_ATHRS17C_SWITCH
 		if (s17c_swt_cfg.chip_detect)
 			ipq_qca8337_switch_init(&s17c_swt_cfg);
-#endif
 #endif
 		eth_register(dev[i]);
 	}
diff --git a/drivers/net/ipq5332/ipq5332_ppe.c b/drivers/net/ipq5332/ipq5332_ppe.c
index 786307d314..90db541548 100644
--- a/drivers/net/ipq5332/ipq5332_ppe.c
+++ b/drivers/net/ipq5332/ipq5332_ppe.c
@@ -21,9 +21,7 @@
 #include <common.h>
 #include <asm/global_data.h>
 #include "ipq5332_ppe.h"
-#ifndef CONFIG_IPQ5332_RUMI
 #include "ipq5332_uniphy.h"
-#endif
 #include <fdtdec.h>
 #include "ipq_phy.h"
 
@@ -269,8 +267,6 @@ void ppe_mac_packet_filter_set(uint32_t port)
 	      (port * MAC_PACKET_FILTER_ADDRESS),
 	      0x80000081);
 }
-
-#ifndef CONFIG_IPQ5332_RUMI
 /*
  * ipq5332_port_mac_clock_reset()
  */
@@ -374,7 +370,6 @@ void ipq5332_10g_r_speed_set(int port, int status)
 	ppe_port_rxmac_status_set(port);
 	ppe_mac_packet_filter_set(port);
 }
-#endif
 
 void ppe_xgmac_speed_set(uint32_t port, int speed)
 {
@@ -456,7 +451,6 @@ void ipq5332_xgmac_sgmiiplus_speed_set(int port, int speed, int status)
 void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex,
 				int status)
 {
-#ifndef CONFIG_IPQ5332_RUMI
 	uint32_t uniphy_index;
 
 	if (port == PORT0)
@@ -466,12 +460,9 @@ void ipq5332_uxsgmii_speed_set(int port, int speed, int duplex,
 
 	ppe_uniphy_usxgmii_autoneg_completed(uniphy_index);
 	ppe_uniphy_usxgmii_speed_set(uniphy_index, speed);
-#endif
 	ppe_xgmac_speed_set(port, speed);
-#ifndef CONFIG_IPQ5332_RUMI
 	ppe_uniphy_usxgmii_duplex_set(uniphy_index, duplex);
 	ppe_uniphy_usxgmii_port_reset(uniphy_index);
-#endif
 	ppe_port_bridge_txmac_set(port, status);
 	ppe_port_txmac_status_set(port);
 	ppe_port_rxmac_status_set(port);
@@ -516,7 +507,6 @@ static void ipq5332_ppe_flow_map_tbl_set(int queue, int port)
  */
 static void ipq5332_ppe_tdm_configuration(void)
 {
-#ifndef CONFIG_IPQ5332_RUMI
 	ipq5332_ppe_reg_write(0xc000, 0x22);
 	ipq5332_ppe_reg_write(0xc010, 0x30);
 	ipq5332_ppe_reg_write(0xc020, 0x21);
@@ -564,19 +554,6 @@ static void ipq5332_ppe_tdm_configuration(void)
 	writel(0x303,(void *)0x3a026100);
 	writel(0x303,(void *)0x3a026104);
 	writel(0x303,(void *)0x3a026108);
-#else
-	ipq5332_ppe_reg_write(0xc000, 0x20);
-	ipq5332_ppe_reg_write(0xc010, 0x32);
-	ipq5332_ppe_reg_write(0xc020, 0x21);
-	ipq5332_ppe_reg_write(0xc030, 0x30);
-	ipq5332_ppe_reg_write(0xc040, 0x22);
-	ipq5332_ppe_reg_write(0xc050, 0x31);
-	ipq5332_ppe_reg_write(0xb000, 0x80000006);
-	ipq5332_ppe_reg_write(0x47a000, 0xfa10);
-	ipq5332_ppe_reg_write(0x47a010, 0xfc21);
-	ipq5332_ppe_reg_write(0x47a020, 0xf902);
-	ipq5332_ppe_reg_write(0x400000, 0x3);
-#endif
 }
 
 /*
@@ -777,11 +754,8 @@ void ipq5332_ppe_interface_mode_init(void)
 		return;
 	}
 
-#ifndef CONFIG_IPQ5332_RUMI
 	ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0);
 	ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1);
-#endif
-
 	/*
 	 * Port1 and Port2 can be used as GMAC or XGMAC.
 	 */