diff --git a/arch/arm/dts/ipq5332-mi01.2.dts b/arch/arm/dts/ipq5332-mi01.2.dts index 4632f339a0..b240b5bb18 100644 --- a/arch/arm/dts/ipq5332-mi01.2.dts +++ b/arch/arm/dts/ipq5332-mi01.2.dts @@ -181,7 +181,7 @@ ess-switch { switch_mac_mode0 = ; switch_mac_mode1 = ; - qca808x_gpio = <16>; + qca808x_gpio = <51>; qca808x_gpio_cnt = <1>; mdc_mdio_gpio = <27 28>; qca8084_switch_enable = <1>; diff --git a/arch/arm/dts/ipq5332-mi01.4.dts b/arch/arm/dts/ipq5332-mi01.4.dts index f1644dcac0..333628c4eb 100644 --- a/arch/arm/dts/ipq5332-mi01.4.dts +++ b/arch/arm/dts/ipq5332-mi01.4.dts @@ -166,7 +166,7 @@ ess-switch { switch_mac_mode0 = ; switch_mac_mode1 = ; - qca808x_gpio = <16>; + qca808x_gpio = <51>; qca808x_gpio_cnt = <1>; mdc_mdio_gpio = <27 28>; napa_gpio = <22>; diff --git a/arch/arm/include/asm/arch-ipq5332/clk.h b/arch/arm/include/asm/arch-ipq5332/clk.h index ff80ff4e15..67b70fea4b 100644 --- a/arch/arm/include/asm/arch-ipq5332/clk.h +++ b/arch/arm/include/asm/arch-ipq5332/clk.h @@ -173,6 +173,7 @@ #define NSS_CC_PORT1_RX_CBCR 0x39B00480 #define NSS_CC_UNIPHY_PORT1_RX_CBCR 0x39B004B4 +#define MDIO_50MHZ_CLK_BASE 0x7a00610 #define GCC_USB_BCR 0x182C000 #define GCC_USB0_MASTER_CMD_RCGR 0x182C004 diff --git a/board/qca/arm/ipq5332/clock.c b/board/qca/arm/ipq5332/clock.c index 8aeaecb69e..4753e28d84 100644 --- a/board/qca/arm/ipq5332/clock.c +++ b/board/qca/arm/ipq5332/clock.c @@ -484,6 +484,16 @@ void mdio_clock_init(void) /* MDIO Master Clock init */ reg_val = readl(GCC_MDIO_MASTER_AHB_CBCR); writel(reg_val | GCC_CBCR_CLK_ENABLE, GCC_MDIO_MASTER_AHB_CBCR); + + /* Enable 50MHZ */ + reg_val = readl(MDIO_50MHZ_CLK_BASE); + reg_val |= BIT(0); + writel(reg_val, MDIO_50MHZ_CLK_BASE); + + reg_val = readl(MDIO_50MHZ_CLK_BASE + 0x10000); + reg_val |= BIT(0); + writel(reg_val, MDIO_50MHZ_CLK_BASE + 0x10000); + } diff --git a/board/qca/arm/ipq5332/ipq5332.c b/board/qca/arm/ipq5332/ipq5332.c index f4d5562a20..17337622d1 100644 --- a/board/qca/arm/ipq5332/ipq5332.c +++ b/board/qca/arm/ipq5332/ipq5332.c @@ -870,6 +870,7 @@ void qca808x_phy_reset_init(void) qca808x_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(qca808x_gpio[i]); cfg = GPIO_OE | GPIO_DRV_8_MA | GPIO_PULL_UP; writel(cfg, qca808x_gpio_base); + gpio_set_value(qca808x_gpio[i], 0x0); } } }