From a148c9c8e4be7a5424dae4fe0c091889be08a346 Mon Sep 17 00:00:00 2001 From: Timple Raj M Date: Fri, 25 Nov 2022 16:15:59 +0530 Subject: [PATCH] arm: dts: ipq5332: update pcie aux clock source as xo The pcie AUX clock source changed to XO as per GCC frequency plan Change-Id: If032831d3a9523ec214a62cbed2950ee5839920e Signed-off-by: Timple Raj M --- arch/arm/include/asm/arch-ipq5332/clk.h | 6 +++--- board/qca/arm/ipq5332/clock.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-ipq5332/clk.h b/arch/arm/include/asm/arch-ipq5332/clk.h index ff80ff4e15..23aead20ec 100644 --- a/arch/arm/include/asm/arch-ipq5332/clk.h +++ b/arch/arm/include/asm/arch-ipq5332/clk.h @@ -314,9 +314,9 @@ #define GCC_PCIE3X1_1_RCHG_CMD_RCGR (GCC_PCIE3X1_1_BASE+0x078) #define GCC_PCIE3X1_1_RCHG_CFG_RCGR (GCC_PCIE3X1_1_BASE+0x07C) -#define GCC_PCIE_AUX_CFG_RCGR_MN_MODE (2 << 12) -#define GCC_PCIE_AUX_CFG_RCGR_SRC_SEL (2 << 8) -#define GCC_PCIE_AUX_CFG_RCGR_SRC_DIV (0x1F << 0) +#define GCC_PCIE_AUX_CFG_RCGR_MN_MODE (0 << 12) +#define GCC_PCIE_AUX_CFG_RCGR_SRC_SEL (0 << 8) /* SRC = XO */ +#define GCC_PCIE_AUX_CFG_RCGR_SRC_DIV (0x17 << 0) #define GCC_PCIE_AXI_CFG_RCGR_SRC_SEL (0x9 << 0) #define GCC_PCIE_AXI_CFG_RCGR_SRC_DIV (2 << 8) diff --git a/board/qca/arm/ipq5332/clock.c b/board/qca/arm/ipq5332/clock.c index b84f00826e..2463efe198 100644 --- a/board/qca/arm/ipq5332/clock.c +++ b/board/qca/arm/ipq5332/clock.c @@ -136,9 +136,9 @@ void pcie_v2_clock_init(int pcie_id) GCC_PCIE_AUX_CFG_RCGR_SRC_SEL | GCC_PCIE_AUX_CFG_RCGR_SRC_DIV); writel(cfg, GCC_PCIE_AUX_CFG_RCGR); - writel(0x1, GCC_PCIE_AUX_M); - writel(0xFFE7, GCC_PCIE_AUX_N); - writel(0xFFE6, GCC_PCIE_AUX_D); + writel(0, GCC_PCIE_AUX_M); + writel(0, GCC_PCIE_AUX_N); + writel(0, GCC_PCIE_AUX_D); writel(CMD_UPDATE, GCC_PCIE_AUX_CMD_RCGR); mdelay(10); writel(ROOT_EN, GCC_PCIE_AUX_CMD_RCGR);