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qca: ipq806x: Moved clock.c to driver/clk/ location.

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Change-Id: Ib4246f2fbe0ab0085827833b93c71835255c5361
Signed-off-by: Aditya Kumar Patra S <apatr@codeaurora.org>
This commit is contained in:
Aditya Kumar Patra S 2016-09-29 11:22:40 +05:30 • committed by Gerrit - the friendly Code Review server
parent d2639a4f08
commit 85671fbdd2
7 changed files with 55 additions and 30 deletions
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1
arch/arm/cpu/armv7/Makefile
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@ -49,7 +49,6 @@ obj-$(CONFIG_OMAP34XX) += omap3/
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/
obj-$(CONFIG_QCA_COMMON) += qca/common/
obj-$(CONFIG_ARCH_IPQ806x) += qca/ipq806x/
obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/

3
arch/arm/cpu/armv7/qca/ipq806x/Kconfig
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@ -1,3 +0,0 @@
config ARCH_IPQ806x
bool "QCA IPQ806x SPECIFIC IPs"

3
arch/arm/cpu/armv7/qca/ipq806x/Makefile
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@ -1,3 +0,0 @@
ccflags-y += -I$(srctree)/board/qca/ipq806x/
obj-y += clock.o

52
arch/arm/include/asm/arch-ipq806x/clk.h Normal file
View file

@ -0,0 +1,52 @@
/*
* Copyright (c) 2012 - 2014 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __PLATFORM_IPQ860X_CLOCK_H_
#define __PLATFORM_IPQ860X_CLOCK_H_
#include <configs/ipq806x.h>
#include <asm/io.h>
#define MSM_CLK_CTL_BASE 0x00900000
#define GSBIn_UART_APPS_MD_REG(n) (MSM_CLK_CTL_BASE + 0x29D0 + (0x20*((n)-1)))
#define GSBIn_UART_APPS_NS_REG(n) (MSM_CLK_CTL_BASE + 0x29D4 + (0x20*((n)-1)))
#define GSBIn_HCLK_CTL_REG(n) (MSM_CLK_CTL_BASE + 0x29C0 + (0x20*((n)-1)))
#define BB_PLL_ENA_SC0_REG (MSM_CLK_CTL_BASE + 0x34C0)
#define PLL_LOCK_DET_STATUS_REG (MSM_CLK_CTL_BASE + 0x03420)
#define MN_MODE_DUAL_EDGE 0x2
#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l)
#define BVAL(m, l, val) (((val) << l) & BM(m, l))
#define Uart_clk_ns_mask (BM(31, 16) | BM(6, 0))
#define Uart_en_mask BIT(11)
#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
/* NS Registers */
#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
(BVAL(n_msb, n_lsb, ~(n-m)) \
| (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
| BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
#define GMAC_CORE_RESET(n) \
((void *)(0x903CBC + ((n) * 0x20)))
#define GMACSEC_CORE_RESET(n) \
((void *)(0x903E28 + ((n - 1) * 4)))
/* Uart specific clock settings */
void uart_pll_vote_clk_enable(void);
void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n,
unsigned int d);
#endif /* __PLATFORM_IPQ860X_CLOCK_H_ */

1
board/qca/ipq806x/ipq806x.c
View file

@ -21,6 +21,7 @@
#include <asm/arch-qcom-common/gpio.h>
#include <asm/arch-qcom-common/smem.h>
#include <asm/arch-ipq806x/msm_ipq806x_gmac.h>
#include <asm/arch-ipq806x/clk.h>
#include "ipq806x.h"
#include "qca_common.h"

1
drivers/clk/Makefile
View file

@ -10,3 +10,4 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_ARCH_IPQ40xx) += ipq40xx_clk.o
obj-$(CONFIG_ARCH_IPQ806x) += ipq806x_clk.o

24
arch/arm/cpu/armv7/qca/ipq806x/clock.c → drivers/clk/ipq806x_clk.c
View file

@ -13,29 +13,7 @@
#include <common.h>
#include <asm/io.h>
#define MSM_CLK_CTL_BASE 0x00900000
#define GSBIn_UART_APPS_MD_REG(n) (MSM_CLK_CTL_BASE + 0x29D0 + (0x20*((n)-1)))
#define GSBIn_UART_APPS_NS_REG(n) (MSM_CLK_CTL_BASE + 0x29D4 + (0x20*((n)-1)))
#define GSBIn_HCLK_CTL_REG(n) (MSM_CLK_CTL_BASE + 0x29C0 + (0x20*((n)-1)))
#define BB_PLL_ENA_SC0_REG (MSM_CLK_CTL_BASE + 0x34C0)
#define PLL_LOCK_DET_STATUS_REG (MSM_CLK_CTL_BASE + 0x03420)
#define MN_MODE_DUAL_EDGE 0x2
#define BIT(s) (1 << s)
#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l)
#define BVAL(m, l, val) (((val) << l) & BM(m, l))
#define Uart_clk_ns_mask (BM(31, 16) | BM(6, 0))
#define Uart_en_mask BIT(11)
#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
/* NS Registers */
#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
(BVAL(n_msb, n_lsb, ~(n-m)) \
| (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
| BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
#include <asm/arch-ipq806x/clk.h>
/**
* uart_pll_vote_clk_enable - enables PLL8