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board: qca: arm: ipq5332: Fix to increase the CDR bandwidth

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This patch increases the CDR bandwidth to pass the
USB 3.0 Rx jitter tolerance test

Change-Id: Id58b71f4078ea5d60ab0b0d7bf93aa0a5d519e3c
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This commit is contained in:
Timple Raj M 2023-05-02 13:26:49 +05:30 • committed by Gerrit - the friendly Code Review server
parent f2660d8f18
commit 75c182c3ec
2 changed files with 17 additions and 0 deletions
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5
board/qca/arm/ipq5332/ipq5332.c
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@ -759,6 +759,11 @@ static void usb_init_ssphy(void __iomem *phybase)
udelay(100);
writel(APB_REG_UPHY_RX_RESCAL_CODE | APB_REG_UPHY_RX_AFE_CAP1 |
APB_REG_UPHY_RX_AFE_RES1, PCIE_USB_COMBO_PHY_CFG_RX_AFE_2);
writel(APB_REG_UPHY_RXD_BIT_WIDTH | APB_REG_UPHY_RX_PLOOP_GAIN |
APB_REG_UPHY_RX_DLF_RATE | APB_UPHY_RX_PLOOP_EN |
APB_REG_UPHY_RX_CDR_EN, PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2);
writel(APB_REG_FLOOP_GAIN, PCIE_USB_COMBO_PHY_CFG_MISC1);
return;
}

12
board/qca/arm/ipq5332/ipq5332.h
View file

@ -110,9 +110,21 @@ extern const add_node_t add_fdt_node[];
#define ATERESET ~BIT(0)
#define PCIE_USB_COMBO_PHY_CFG_RX_AFE_2 0x4B07C4
#define PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2 0x4B07E8
#define PCIE_USB_COMBO_PHY_CFG_MISC1 0x4B0214
#define APB_REG_UPHY_RX_RESCAL_CODE (16 << 8)
#define APB_REG_UPHY_RX_AFE_CAP1 (7 << 4)
#define APB_REG_UPHY_RX_AFE_RES1 (6 << 0)
#define APB_REG_UPHY_RXD_BIT_WIDTH (2 << 0)
#define APB_REG_UPHY_RX_PLOOP_GAIN (4 << 4)
#define APB_REG_UPHY_RX_DLF_RATE (1 << 8)
#define APB_UPHY_RX_PLOOP_EN (1 << 12)
#define APB_REG_UPHY_RX_CDR_EN (1 << 13)
#define APB_REG_FLOOP_GAIN (3 << 0)
#define TCSR_SOC_HW_VERSION_REG 0x194D000
/*