From 6173c50c846567aa83e097e7a22b4e23990a80d3 Mon Sep 17 00:00:00 2001 From: Rajkumar Ayyasamy Date: Wed, 7 Mar 2018 15:02:02 +0530 Subject: [PATCH] ipq40xx: Changed the assert sequence for pcie linkup Changed the assert and deassert sequence to enable the pcie linkup for peripheral specific devices. Change-Id: I2f93f818fe9f85ffa43fb5dff1a9cc67ae393183 Signed-off-by: Rajkumar Ayyasamy --- drivers/pci/pci_ipq.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/pci/pci_ipq.c b/drivers/pci/pci_ipq.c index 0b616ccebf..a5a4a7acf3 100644 --- a/drivers/pci/pci_ipq.c +++ b/drivers/pci/pci_ipq.c @@ -644,6 +644,16 @@ void pci_controller_init_v1(struct ipq_pcie *pcie) { uint32_t val; + /* Assert cc_pcie20_mstr_axi_ares */ + val = readl(pcie->pci_rst.start); + val |= PCIE_RST_CTRL_AXI_M_ARES; + writel(val, pcie->pci_rst.start); + + /* Assert cc_pcie20_slv_axi_ares */ + val = readl(pcie->pci_rst.start); + val |= PCIE_RST_CTRL_AXI_S_ARES; + writel(val, pcie->pci_rst.start); + /* Assert cc_pcie20_core_ares */ writel(PCIE_RST_CTRL_PIPE_ARES, pcie->pci_rst.start); @@ -657,31 +667,21 @@ void pci_controller_init_v1(struct ipq_pcie *pcie) val |= PCIE_RST_CTRL_PIPE_PHY_AHB_ARES; writel(val, pcie->pci_rst.start); - gpio_set_value(pcie->rst_gpio, GPIO_OUT_LOW); - - /* Assert cc_pcie20_mstr_axi_ares */ - val = readl(pcie->pci_rst.start); - val |= PCIE_RST_CTRL_AXI_M_ARES; - writel(val, pcie->pci_rst.start); - /* Assert cc_pcie20_mstr_sticky_ares */ val = readl(pcie->pci_rst.start); val |= PCIE_RST_CTRL_AXI_M_STICKY_ARES; writel(val, pcie->pci_rst.start); - /* Assert cc_pcie20_slv_axi_ares */ - val = readl(pcie->pci_rst.start); - val |= PCIE_RST_CTRL_AXI_S_ARES; - writel(val, pcie->pci_rst.start); + gpio_set_value(pcie->rst_gpio, GPIO_OUT_LOW); /* Assert cc_pcie20_ahb_ares; */ val = readl(pcie->pci_rst.start); val |= PCIE_RST_CTRL_AHB_ARES; writel(val, pcie->pci_rst.start); - /* DeAssert cc_pcie20_phy_ahb_ares */ + /* DeAssert cc_pcie20_ahb_ares */ val = readl(pcie->pci_rst.start); - val &= ~(PCIE_RST_CTRL_AHB_ARES); + val &= ~(PCIE_RST_CTRL_PIPE_PHY_AHB_ARES); writel(val, pcie->pci_rst.start); /* DeAssert cc_pcie20_pciephy_phy_ares*/ @@ -713,9 +713,9 @@ void pci_controller_init_v1(struct ipq_pcie *pcie) val &= ~(PCIE_RST_CTRL_AXI_S_ARES); writel(val, pcie->pci_rst.start); - /* DeAssert cc_pcie20_ahb_ares */ + /* DeAssert cc_pcie20_phy_ahb_ares */ val = readl(pcie->pci_rst.start); - val &= ~(PCIE_RST_CTRL_PIPE_PHY_AHB_ARES); + val &= ~(PCIE_RST_CTRL_AHB_ARES); writel(val, pcie->pci_rst.start); }