mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-14 21:10:27 +01:00
Merge "ipq5018: Add spi nor support"
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commit
5cab6b814f
6 changed files with 184 additions and 146 deletions
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@ -14,11 +14,11 @@
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/dts-v1/;
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#include "ipq5018-soc.dtsi"
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/ {
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model ="QCA, IPQ5018-EMULATION";
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compatible = "qca,ipq5018", "qca,ipq5018-emulation";
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machid = <0x08010000>;
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model ="QCA, IPQ5018-EMULATION";
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compatible = "qca,ipq5018", "qca,ipq5018-emulation";
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machid = <0x08010000>;
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aliases {
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console = "/serial@78AF000";
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};
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aliases {
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console = "/serial@78AF000";
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};
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};
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@ -16,11 +16,11 @@
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/ {
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serial@78AF000 {
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compatible = "qca,ipq-uartdm";
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reg = <0x78af000 0x200>;
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id = <2>;
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bit_rate = <0xff>;
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serial@78AF000 {
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compatible = "qca,ipq-uartdm";
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reg = <0x78af000 0x200>;
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id = <2>;
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bit_rate = <0xff>;
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status = "ok";
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serial_gpio {
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gpio1 {
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@ -33,7 +33,6 @@
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sr_en = <GPIO_SR_DISABLE>;
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pu_res =<GPIO_PULL_RES0>;
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pu = <1>;
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};
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gpio2 {
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gpio = <21>;
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@ -47,14 +46,22 @@
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pu = <1>;
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};
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};
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};
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};
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timer {
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gcnt_base = <0x4a1000>;
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gcnt_cntcv_lo = <0x4a2000>;
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gcnt_cntcv_hi = <0x4a2004>;
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gpt_freq_hz = <48000000>;
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timer_load_val = <0x00FFFFFF 0xFFFFFFFF>;
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};
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timer {
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gcnt_base = <0x4a1000>;
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gcnt_cntcv_lo = <0x4a2000>;
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gcnt_cntcv_hi = <0x4a2004>;
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gpt_freq_hz = <48000000>;
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timer_load_val = <0x00FFFFFF 0xFFFFFFFF>;
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};
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spi {
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status = "ok";
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compatible = "qcom,spi-qup-v2.7.0";
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wr_pipe_0 = <12>;
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rd_pipe_0 = <13>;
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spi_gpio {};
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};
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};
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@ -23,6 +23,7 @@
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#include <ipq5018.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern int ipq_spi_init(u16);
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void uart1_configure_mux(void)
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{
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@ -49,9 +50,9 @@ void uart1_configure_mux(void)
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void uart1_set_rate_mnd(unsigned int m,
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unsigned int n, unsigned int two_d)
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{
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writel(m, GCC_BLSP1_UART1_APPS_M);
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writel(NOT_N_MINUS_M(n, m), GCC_BLSP1_UART1_APPS_N);
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writel(NOT_2D(two_d), GCC_BLSP1_UART1_APPS_D);
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writel(m, GCC_BLSP1_UART1_APPS_M);
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writel(NOT_N_MINUS_M(n, m), GCC_BLSP1_UART1_APPS_N);
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writel(NOT_2D(two_d), GCC_BLSP1_UART1_APPS_D);
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}
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int uart1_trigger_update(void)
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@ -81,11 +82,11 @@ void reset_board(void)
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void uart1_toggle_clock(void)
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{
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unsigned long cbcr_val;
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unsigned long cbcr_val;
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cbcr_val = readl(GCC_BLSP1_UART1_APPS_CBCR);
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cbcr_val |= UART1_CBCR_CLK_ENABLE;
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writel(cbcr_val, GCC_BLSP1_UART1_APPS_CBCR);
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cbcr_val = readl(GCC_BLSP1_UART1_APPS_CBCR);
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cbcr_val |= UART1_CBCR_CLK_ENABLE;
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writel(cbcr_val, GCC_BLSP1_UART1_APPS_CBCR);
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}
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void uart1_clock_config(unsigned int m,
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@ -104,33 +105,40 @@ void qca_serial_init(struct ipq_serial_platdata *plat)
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writel(1, GCC_BLSP1_UART1_APPS_CBCR);
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node = fdt_path_offset(gd->fdt_blob, "/serial@78AF000/serial_gpio");
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if (node < 0) {
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printf("Could not find serial_gpio node\n");
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return;
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}
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printf("Could not find serial_gpio node\n");
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return;
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}
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if (plat->port_id == 1) {
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uart1_node = fdt_path_offset(gd->fdt_blob, "uart1");
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if (uart1_node < 0) {
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printf("Could not find uart1 node\n");
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return;
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}
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node = fdt_subnode_offset(gd->fdt_blob,
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uart1_node, "serial_gpio");
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uart1_clock_config(plat->m_value, plat->n_value, plat->d_value);
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writel(1, GCC_BLSP1_UART1_APPS_CBCR);
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}
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if (plat->port_id == 1) {
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uart1_node = fdt_path_offset(gd->fdt_blob, "uart1");
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if (uart1_node < 0) {
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printf("Could not find uart1 node\n");
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return;
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}
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node = fdt_subnode_offset(gd->fdt_blob,
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uart1_node, "serial_gpio");
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uart1_clock_config(plat->m_value, plat->n_value, plat->d_value);
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writel(1, GCC_BLSP1_UART1_APPS_CBCR);
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}
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qca_gpio_init(node);
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qca_gpio_init(node);
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}
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void reset_crashdump(void)
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{
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return;
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return;
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}
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void board_nand_init(void)
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{
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return;
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#ifdef CONFIG_QCA_SPI
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int gpio_node;
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gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
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if (gpio_node >= 0) {
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qca_gpio_init(gpio_node);
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ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX);
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}
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#endif
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}
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void enable_caches(void)
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@ -59,33 +59,34 @@
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#define KERNEL_AUTH_CMD 0x13
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#define SCM_CMD_SEC_AUTH 0x1F
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struct smem_ram_ptn {
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char name[16];
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unsigned long long start;
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unsigned long long size;
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/* RAM Partition attribute: READ_ONLY, READWRITE etc. */
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unsigned attr;
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/* RAM Partition attribute: READ_ONLY, READWRITE etc. */
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unsigned attr;
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/* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
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unsigned category;
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/* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
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unsigned category;
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/* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
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unsigned domain;
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/* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
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unsigned domain;
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/* RAM Partition type: system, bootloader, appsboot, apps etc. */
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unsigned type;
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/* RAM Partition type: system, bootloader, appsboot, apps etc. */
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unsigned type;
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/* reserved for future expansion without changing version number */
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unsigned reserved2, reserved3, reserved4, reserved5;
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/* reserved for future expansion without changing version number */
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unsigned reserved2, reserved3, reserved4, reserved5;
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} __attribute__ ((__packed__));
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__weak void aquantia_phy_reset_init_done(void) {}
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__weak void aquantia_phy_reset_init(void) {}
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struct smem_ram_ptable {
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#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
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#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
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#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
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#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
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unsigned magic[2];
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unsigned version;
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unsigned reserved1;
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@ -99,24 +100,24 @@ void reset_crashdump(void);
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void reset_board(void);
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typedef enum {
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SMEM_SPINLOCK_ARRAY = 7,
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SMEM_AARM_PARTITION_TABLE = 9,
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SMEM_HW_SW_BUILD_ID = 137,
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SMEM_USABLE_RAM_PARTITION_TABLE = 402,
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SMEM_POWER_ON_STATUS_INFO = 403,
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SMEM_MACHID_INFO_LOCATION = 425,
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SMEM_IMAGE_VERSION_TABLE = 469,
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SMEM_BOOT_FLASH_TYPE = 498,
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SMEM_BOOT_FLASH_INDEX = 499,
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SMEM_BOOT_FLASH_CHIP_SELECT = 500,
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SMEM_BOOT_FLASH_BLOCK_SIZE = 501,
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SMEM_BOOT_FLASH_DENSITY = 502,
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SMEM_BOOT_DUALPARTINFO = 503,
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SMEM_PARTITION_TABLE_OFFSET = 504,
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SMEM_SPI_FLASH_ADDR_LEN = 505,
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SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
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SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN,
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SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1,
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SMEM_SPINLOCK_ARRAY = 7,
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SMEM_AARM_PARTITION_TABLE = 9,
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SMEM_HW_SW_BUILD_ID = 137,
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SMEM_USABLE_RAM_PARTITION_TABLE = 402,
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SMEM_POWER_ON_STATUS_INFO = 403,
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SMEM_MACHID_INFO_LOCATION = 425,
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SMEM_IMAGE_VERSION_TABLE = 469,
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SMEM_BOOT_FLASH_TYPE = 498,
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SMEM_BOOT_FLASH_INDEX = 499,
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SMEM_BOOT_FLASH_CHIP_SELECT = 500,
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SMEM_BOOT_FLASH_BLOCK_SIZE = 501,
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SMEM_BOOT_FLASH_DENSITY = 502,
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SMEM_BOOT_DUALPARTINFO = 503,
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SMEM_PARTITION_TABLE_OFFSET = 504,
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SMEM_SPI_FLASH_ADDR_LEN = 505,
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SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
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SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN,
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SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1,
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} smem_mem_type_t;
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#endif /* _IPQ5018_CDP_H_ */
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@ -36,6 +36,8 @@ ifdef CONFIG_QCA_SPI
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obj-$(CONFIG_ARCH_IPQ40xx) += qca_qup_spi_bam.o
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obj-$(CONFIG_ARCH_IPQ807x) += qca_qup_spi_bam.o
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obj-$(CONFIG_ARCH_IPQ6018) += qca_qup_spi_bam.o
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obj-$(CONFIG_ARCH_IPQ5018) += qca_qup_spi_bam.o
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obj-$(CONFIG_ARCH_IPQ806x) += ipq_spi.o
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endif
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obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
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@ -21,16 +21,15 @@
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#define CONFIG_IPQ5018
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#define IPQ5018_EMULATION
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define CONFIG_IPQ5018_UART
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
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#define CONFIG_ENV_IS_NOWHERE 1
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#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
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/*
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*Size of malloc() pool
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@ -39,56 +38,56 @@
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_CONS_INDEX 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */
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/*
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svc_sp --> --------------
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irq_sp --> | |
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fiq_sp --> | |
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bd --> | |
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gd --> | |
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pgt --> | |
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malloc --> | |
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text_base --> |------------|
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svc_sp --> --------------
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irq_sp --> | |
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fiq_sp --> | |
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bd --> | |
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gd --> | |
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pgt --> | |
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malloc --> | |
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text_base --> |------------|
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*/
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\
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CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\
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GENERATED_BD_INFO_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\
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CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\
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GENERATED_BD_INFO_SIZE)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define TLMM_BASE 0x01000000
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#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000)
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#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000)
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#define TLMM_BASE 0x01000000
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#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000)
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#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000)
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_TEXT_BASE 0x8A900000
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000
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#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20))
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_TEXT_BASE 0x8A900000
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000
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#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20))
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#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE
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#define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE
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#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100)
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#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE
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#define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE
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#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100)
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#define CONFIG_OF_COMBINE 1
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#define CONFIG_OF_COMBINE 1
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|
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#define CONFIG_QCA_SMEM_BASE 0x8AB00000
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#define CONFIG_QCA_SMEM_BASE 0x8AB00000
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#define CONFIG_IPQ_FDT_HIGH 0x8A400000
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#define CONFIG_IPQ_NO_MACS 6
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#define CONFIG_ENV_IS_IN_SPI_FLASH 1
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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||||
#define CONFIG_IPQ_FDT_HIGH 0x8A400000
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#define CONFIG_IPQ_NO_MACS 6
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#define CONFIG_ENV_IS_IN_SPI_FLASH 1
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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|
||||
/*
|
||||
* IPQ_TFTP_MIN_ADDR: Starting address of Linux HLOS region.
|
||||
|
|
@ -96,9 +95,9 @@
|
|||
* address of WLAN Area.
|
||||
* TFTP file can only be written in Linux HLOS region and WLAN AREA.
|
||||
*/
|
||||
#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20))
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#define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21))
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#define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size)
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#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20))
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#define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21))
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#define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size)
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|
||||
#ifndef __ASSEMBLY__
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#include <compiler.h>
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||||
|
|
@ -107,13 +106,13 @@ extern loff_t board_env_range;
|
|||
extern loff_t board_env_size;
|
||||
#endif
|
||||
|
||||
#define CONFIG_IPQ5018_ENV 1
|
||||
#define CONFIG_ENV_OFFSET board_env_offset
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX
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||||
#define CONFIG_ENV_RANGE board_env_range
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (1024 << 10))
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#define CONFIG_IPQ5018_ENV 1
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||||
#define CONFIG_ENV_OFFSET board_env_offset
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX
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||||
#define CONFIG_ENV_RANGE board_env_range
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||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (1024 << 10))
|
||||
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
|
||||
/*
|
||||
* NAND Flash Configs
|
||||
|
|
@ -129,41 +128,62 @@ extern loff_t board_env_size;
|
|||
#define CONFIG_SYS_NAND_SELF_INIT
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/*
|
||||
* SPI Flash Configs
|
||||
*/
|
||||
#define CONFIG_QCA_SPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SPI_FLASH_MACRONIX
|
||||
#define CONFIG_SPI_FLASH_GIGADEVICE
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED (48 * 1000 * 1000)
|
||||
#define CONFIG_SPI_FLASH_BAR 1
|
||||
#define CONFIG_SPI_FLASH_USE_4K_SECTORS
|
||||
#define CONFIG_IPQ_4B_ADDR_SWITCH_REQD
|
||||
|
||||
#define CONFIG_QUP_SPI_USE_DMA 0
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_QCA_BAM 1
|
||||
/*
|
||||
* Expose SPI driver as a pseudo NAND driver to make use
|
||||
* of U-Boot's MTD framework.
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \
|
||||
CONFIG_IPQ_MAX_SPI_DEVICE
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \
|
||||
CONFIG_IPQ_MAX_SPI_DEVICE
|
||||
|
||||
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
|
||||
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
|
||||
|
||||
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
|
||||
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
|
||||
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
|
||||
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
|
||||
|
||||
#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX
|
||||
#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
|
||||
#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX
|
||||
#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
|
||||
|
||||
#define QCA_SPI_NOR_DEVICE "spi0.0"
|
||||
#define CONFIG_QUP_SPI_USE_DMA 1
|
||||
#define QCA_SPI_NOR_DEVICE "spi0.0"
|
||||
|
||||
/*
|
||||
* U-Boot Env Configs
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
|
||||
/* NSS firmware loaded using bootm */
|
||||
#define CONFIG_BOOTCOMMAND "bootm"
|
||||
#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8"
|
||||
#define QCA_ROOT_FS_PART_NAME "rootfs"
|
||||
#define CONFIG_BOOTCOMMAND "bootm"
|
||||
#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8"
|
||||
#define QCA_ROOT_FS_PART_NAME "rootfs"
|
||||
|
||||
#define CONFIG_BOOTDELAY 2
|
||||
#define CONFIG_BOOTDELAY 2
|
||||
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define NUM_ALT_PARTITION 16
|
||||
#define NUM_ALT_PARTITION 16
|
||||
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_RBTREE
|
||||
|
|
@ -174,14 +194,14 @@ extern loff_t board_env_size;
|
|||
* Below Configs need to be updated after enabling reset_crashdump
|
||||
* Included now to avoid build failure
|
||||
*/
|
||||
#define SET_MAGIC 0x1
|
||||
#define CLEAR_MAGIC 0x0
|
||||
#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9
|
||||
#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10
|
||||
#define SCM_CMD_TZ_PSHOLD 0x15
|
||||
#define SET_MAGIC 0x1
|
||||
#define CLEAR_MAGIC 0x0
|
||||
#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9
|
||||
#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10
|
||||
#define SCM_CMD_TZ_PSHOLD 0x15
|
||||
/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
|
||||
* Cache flush and invalidation based on L1 cache, so the cache line
|
||||
* size is configured to 64 */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
#endif /* _IPQ5018_H */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue