From 5951991989a555be0a1360a2c57d15380e28e25d Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Thu, 17 Oct 2019 13:48:41 +0530 Subject: [PATCH 1/2] ipq5018: Fixing whitespace errors Change-Id: I8c3c6cb436344cec2211cd53281d757e68bc0a6b Signed-off-by: Vandhiadevan Karunamoorthy --- arch/arm/dts/ipq5018-emulation.dts | 12 +-- arch/arm/dts/ipq5018-soc.dtsi | 27 +++--- board/qca/arm/ipq5018/ipq5018.c | 46 ++++----- board/qca/arm/ipq5018/ipq5018.h | 61 ++++++------ include/configs/ipq5018.h | 145 +++++++++++++++-------------- 5 files changed, 146 insertions(+), 145 deletions(-) diff --git a/arch/arm/dts/ipq5018-emulation.dts b/arch/arm/dts/ipq5018-emulation.dts index 6dee11f0da..03bf807fd4 100644 --- a/arch/arm/dts/ipq5018-emulation.dts +++ b/arch/arm/dts/ipq5018-emulation.dts @@ -14,11 +14,11 @@ /dts-v1/; #include "ipq5018-soc.dtsi" / { - model ="QCA, IPQ5018-EMULATION"; - compatible = "qca,ipq5018", "qca,ipq5018-emulation"; - machid = <0x08010000>; + model ="QCA, IPQ5018-EMULATION"; + compatible = "qca,ipq5018", "qca,ipq5018-emulation"; + machid = <0x08010000>; - aliases { - console = "/serial@78AF000"; - }; + aliases { + console = "/serial@78AF000"; + }; }; diff --git a/arch/arm/dts/ipq5018-soc.dtsi b/arch/arm/dts/ipq5018-soc.dtsi index e82c122daf..b179f89356 100644 --- a/arch/arm/dts/ipq5018-soc.dtsi +++ b/arch/arm/dts/ipq5018-soc.dtsi @@ -16,11 +16,11 @@ / { - serial@78AF000 { - compatible = "qca,ipq-uartdm"; - reg = <0x78af000 0x200>; - id = <2>; - bit_rate = <0xff>; + serial@78AF000 { + compatible = "qca,ipq-uartdm"; + reg = <0x78af000 0x200>; + id = <2>; + bit_rate = <0xff>; status = "ok"; serial_gpio { gpio1 { @@ -33,7 +33,6 @@ sr_en = ; pu_res =; pu = <1>; - }; gpio2 { gpio = <21>; @@ -47,14 +46,14 @@ pu = <1>; }; }; - }; + }; - timer { - gcnt_base = <0x4a1000>; - gcnt_cntcv_lo = <0x4a2000>; - gcnt_cntcv_hi = <0x4a2004>; - gpt_freq_hz = <48000000>; - timer_load_val = <0x00FFFFFF 0xFFFFFFFF>; - }; + timer { + gcnt_base = <0x4a1000>; + gcnt_cntcv_lo = <0x4a2000>; + gcnt_cntcv_hi = <0x4a2004>; + gpt_freq_hz = <48000000>; + timer_load_val = <0x00FFFFFF 0xFFFFFFFF>; + }; }; diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c index 96d9824830..b7c87d467e 100644 --- a/board/qca/arm/ipq5018/ipq5018.c +++ b/board/qca/arm/ipq5018/ipq5018.c @@ -49,9 +49,9 @@ void uart1_configure_mux(void) void uart1_set_rate_mnd(unsigned int m, unsigned int n, unsigned int two_d) { - writel(m, GCC_BLSP1_UART1_APPS_M); - writel(NOT_N_MINUS_M(n, m), GCC_BLSP1_UART1_APPS_N); - writel(NOT_2D(two_d), GCC_BLSP1_UART1_APPS_D); + writel(m, GCC_BLSP1_UART1_APPS_M); + writel(NOT_N_MINUS_M(n, m), GCC_BLSP1_UART1_APPS_N); + writel(NOT_2D(two_d), GCC_BLSP1_UART1_APPS_D); } int uart1_trigger_update(void) @@ -81,11 +81,11 @@ void reset_board(void) void uart1_toggle_clock(void) { - unsigned long cbcr_val; + unsigned long cbcr_val; - cbcr_val = readl(GCC_BLSP1_UART1_APPS_CBCR); - cbcr_val |= UART1_CBCR_CLK_ENABLE; - writel(cbcr_val, GCC_BLSP1_UART1_APPS_CBCR); + cbcr_val = readl(GCC_BLSP1_UART1_APPS_CBCR); + cbcr_val |= UART1_CBCR_CLK_ENABLE; + writel(cbcr_val, GCC_BLSP1_UART1_APPS_CBCR); } void uart1_clock_config(unsigned int m, @@ -104,28 +104,28 @@ void qca_serial_init(struct ipq_serial_platdata *plat) writel(1, GCC_BLSP1_UART1_APPS_CBCR); node = fdt_path_offset(gd->fdt_blob, "/serial@78AF000/serial_gpio"); if (node < 0) { - printf("Could not find serial_gpio node\n"); - return; - } + printf("Could not find serial_gpio node\n"); + return; + } - if (plat->port_id == 1) { - uart1_node = fdt_path_offset(gd->fdt_blob, "uart1"); - if (uart1_node < 0) { - printf("Could not find uart1 node\n"); - return; - } - node = fdt_subnode_offset(gd->fdt_blob, - uart1_node, "serial_gpio"); - uart1_clock_config(plat->m_value, plat->n_value, plat->d_value); - writel(1, GCC_BLSP1_UART1_APPS_CBCR); - } + if (plat->port_id == 1) { + uart1_node = fdt_path_offset(gd->fdt_blob, "uart1"); + if (uart1_node < 0) { + printf("Could not find uart1 node\n"); + return; + } + node = fdt_subnode_offset(gd->fdt_blob, + uart1_node, "serial_gpio"); + uart1_clock_config(plat->m_value, plat->n_value, plat->d_value); + writel(1, GCC_BLSP1_UART1_APPS_CBCR); + } - qca_gpio_init(node); + qca_gpio_init(node); } void reset_crashdump(void) { - return; + return; } void board_nand_init(void) diff --git a/board/qca/arm/ipq5018/ipq5018.h b/board/qca/arm/ipq5018/ipq5018.h index 2af26fcc5e..55032f24ef 100644 --- a/board/qca/arm/ipq5018/ipq5018.h +++ b/board/qca/arm/ipq5018/ipq5018.h @@ -59,33 +59,34 @@ #define KERNEL_AUTH_CMD 0x13 #define SCM_CMD_SEC_AUTH 0x1F + struct smem_ram_ptn { char name[16]; unsigned long long start; unsigned long long size; - /* RAM Partition attribute: READ_ONLY, READWRITE etc. */ - unsigned attr; + /* RAM Partition attribute: READ_ONLY, READWRITE etc. */ + unsigned attr; - /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */ - unsigned category; + /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */ + unsigned category; - /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */ - unsigned domain; + /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */ + unsigned domain; - /* RAM Partition type: system, bootloader, appsboot, apps etc. */ - unsigned type; + /* RAM Partition type: system, bootloader, appsboot, apps etc. */ + unsigned type; - /* reserved for future expansion without changing version number */ - unsigned reserved2, reserved3, reserved4, reserved5; + /* reserved for future expansion without changing version number */ + unsigned reserved2, reserved3, reserved4, reserved5; } __attribute__ ((__packed__)); __weak void aquantia_phy_reset_init_done(void) {} __weak void aquantia_phy_reset_init(void) {} struct smem_ram_ptable { - #define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8 - #define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2 + #define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8 + #define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2 unsigned magic[2]; unsigned version; unsigned reserved1; @@ -99,24 +100,24 @@ void reset_crashdump(void); void reset_board(void); typedef enum { - SMEM_SPINLOCK_ARRAY = 7, - SMEM_AARM_PARTITION_TABLE = 9, - SMEM_HW_SW_BUILD_ID = 137, - SMEM_USABLE_RAM_PARTITION_TABLE = 402, - SMEM_POWER_ON_STATUS_INFO = 403, - SMEM_MACHID_INFO_LOCATION = 425, - SMEM_IMAGE_VERSION_TABLE = 469, - SMEM_BOOT_FLASH_TYPE = 498, - SMEM_BOOT_FLASH_INDEX = 499, - SMEM_BOOT_FLASH_CHIP_SELECT = 500, - SMEM_BOOT_FLASH_BLOCK_SIZE = 501, - SMEM_BOOT_FLASH_DENSITY = 502, - SMEM_BOOT_DUALPARTINFO = 503, - SMEM_PARTITION_TABLE_OFFSET = 504, - SMEM_SPI_FLASH_ADDR_LEN = 505, - SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY, - SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN, - SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1, + SMEM_SPINLOCK_ARRAY = 7, + SMEM_AARM_PARTITION_TABLE = 9, + SMEM_HW_SW_BUILD_ID = 137, + SMEM_USABLE_RAM_PARTITION_TABLE = 402, + SMEM_POWER_ON_STATUS_INFO = 403, + SMEM_MACHID_INFO_LOCATION = 425, + SMEM_IMAGE_VERSION_TABLE = 469, + SMEM_BOOT_FLASH_TYPE = 498, + SMEM_BOOT_FLASH_INDEX = 499, + SMEM_BOOT_FLASH_CHIP_SELECT = 500, + SMEM_BOOT_FLASH_BLOCK_SIZE = 501, + SMEM_BOOT_FLASH_DENSITY = 502, + SMEM_BOOT_DUALPARTINFO = 503, + SMEM_PARTITION_TABLE_OFFSET = 504, + SMEM_SPI_FLASH_ADDR_LEN = 505, + SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY, + SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN, + SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1, } smem_mem_type_t; #endif /* _IPQ5018_CDP_H_ */ diff --git a/include/configs/ipq5018.h b/include/configs/ipq5018.h index 619b60d228..632054ef6b 100644 --- a/include/configs/ipq5018.h +++ b/include/configs/ipq5018.h @@ -21,16 +21,16 @@ #define CONFIG_IPQ5018 #define IPQ5018_EMULATION #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_IPQ5018_UART -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_BOOTM_LEN 0x1000000 +#define CONFIG_SYS_BOOTM_LEN 0x1000000 -#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */ -#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */ +#define CONFIG_ENV_IS_NOWHERE 1 /* *Size of malloc() pool @@ -39,56 +39,56 @@ /* * select serial console configuration */ -#define CONFIG_CONS_INDEX 1 +#define CONFIG_CONS_INDEX 1 /* allow to overwrite serial and ethaddr */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} -#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */ /* - svc_sp --> -------------- - irq_sp --> | | - fiq_sp --> | | - bd --> | | - gd --> | | - pgt --> | | - malloc --> | | - text_base --> |------------| + svc_sp --> -------------- + irq_sp --> | | + fiq_sp --> | | + bd --> | | + gd --> | | + pgt --> | | + malloc --> | | + text_base --> |------------| */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\ - CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\ - GENERATED_BD_INFO_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\ + CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\ + GENERATED_BD_INFO_SIZE) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) -#define TLMM_BASE 0x01000000 -#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000) -#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000) +#define TLMM_BASE 0x01000000 +#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000) +#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000) -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_TEXT_BASE 0x8A900000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 -#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20)) +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_TEXT_BASE 0x8A900000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20)) -#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE -#define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE -#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100) +#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE +#define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE +#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100) -#define CONFIG_OF_COMBINE 1 +#define CONFIG_OF_COMBINE 1 -#define CONFIG_QCA_SMEM_BASE 0x8AB00000 +#define CONFIG_QCA_SMEM_BASE 0x8AB00000 -#define CONFIG_IPQ_FDT_HIGH 0x8A400000 -#define CONFIG_IPQ_NO_MACS 6 -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 -#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_IPQ_FDT_HIGH 0x8A400000 +#define CONFIG_IPQ_NO_MACS 6 +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (64 * 1024) /* * IPQ_TFTP_MIN_ADDR: Starting address of Linux HLOS region. @@ -96,9 +96,9 @@ * address of WLAN Area. * TFTP file can only be written in Linux HLOS region and WLAN AREA. */ -#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20)) -#define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21)) -#define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size) +#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20)) +#define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21)) +#define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size) #ifndef __ASSEMBLY__ #include @@ -107,13 +107,13 @@ extern loff_t board_env_range; extern loff_t board_env_size; #endif -#define CONFIG_IPQ5018_ENV 1 -#define CONFIG_ENV_OFFSET board_env_offset -#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX -#define CONFIG_ENV_RANGE board_env_range -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (1024 << 10)) +#define CONFIG_IPQ5018_ENV 1 +#define CONFIG_ENV_OFFSET board_env_offset +#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX +#define CONFIG_ENV_RANGE board_env_range +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (1024 << 10)) -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_IN_NAND 1 /* * NAND Flash Configs @@ -129,41 +129,42 @@ extern loff_t board_env_size; #define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_SYS_NAND_ONFI_DETECTION + /* * Expose SPI driver as a pseudo NAND driver to make use * of U-Boot's MTD framework. */ -#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \ - CONFIG_IPQ_MAX_SPI_DEVICE +#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \ + CONFIG_IPQ_MAX_SPI_DEVICE -#define CONFIG_IPQ_MAX_NAND_DEVICE 1 -#define CONFIG_IPQ_MAX_SPI_DEVICE 1 +#define CONFIG_IPQ_MAX_NAND_DEVICE 1 +#define CONFIG_IPQ_MAX_SPI_DEVICE 1 -#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0 -#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1 +#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0 +#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1 -#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX -#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX +#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX +#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX -#define QCA_SPI_NOR_DEVICE "spi0.0" -#define CONFIG_QUP_SPI_USE_DMA 1 +#define QCA_SPI_NOR_DEVICE "spi0.0" +#define CONFIG_QUP_SPI_USE_DMA 1 /* * U-Boot Env Configs */ -#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_LIBFDT 1 /* NSS firmware loaded using bootm */ -#define CONFIG_BOOTCOMMAND "bootm" -#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8" -#define QCA_ROOT_FS_PART_NAME "rootfs" +#define CONFIG_BOOTCOMMAND "bootm" +#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8" +#define QCA_ROOT_FS_PART_NAME "rootfs" -#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTDELAY 2 #define CONFIG_MTD_DEVICE #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS -#define NUM_ALT_PARTITION 16 +#define NUM_ALT_PARTITION 16 #define CONFIG_CMD_UBI #define CONFIG_RBTREE @@ -174,14 +175,14 @@ extern loff_t board_env_size; * Below Configs need to be updated after enabling reset_crashdump * Included now to avoid build failure */ -#define SET_MAGIC 0x1 -#define CLEAR_MAGIC 0x0 -#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9 -#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10 -#define SCM_CMD_TZ_PSHOLD 0x15 +#define SET_MAGIC 0x1 +#define CLEAR_MAGIC 0x0 +#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9 +#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10 +#define SCM_CMD_TZ_PSHOLD 0x15 /* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes * Cache flush and invalidation based on L1 cache, so the cache line * size is configured to 64 */ -#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CACHELINE_SIZE 64 #endif /* _IPQ5018_H */ From 73712e5b7d1b2ae8a2d94a31b51c62c5f92b7b60 Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Thu, 17 Oct 2019 16:53:45 +0530 Subject: [PATCH 2/2] ipq5018: Add spi nor support Change-Id: I1191f2cab63f09fa9c69f417d9cd3050e7a928e3 Signed-off-by: Vandhiadevan Karunamoorthy --- arch/arm/dts/ipq5018-soc.dtsi | 8 ++++++++ board/qca/arm/ipq5018/ipq5018.c | 10 +++++++++- drivers/spi/Makefile | 2 ++ include/configs/ipq5018.h | 23 +++++++++++++++++++++-- 4 files changed, 40 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/ipq5018-soc.dtsi b/arch/arm/dts/ipq5018-soc.dtsi index b179f89356..e425396fb5 100644 --- a/arch/arm/dts/ipq5018-soc.dtsi +++ b/arch/arm/dts/ipq5018-soc.dtsi @@ -56,4 +56,12 @@ timer_load_val = <0x00FFFFFF 0xFFFFFFFF>; }; + spi { + status = "ok"; + compatible = "qcom,spi-qup-v2.7.0"; + wr_pipe_0 = <12>; + rd_pipe_0 = <13>; + spi_gpio {}; + }; + }; diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c index b7c87d467e..0efbd86ccf 100644 --- a/board/qca/arm/ipq5018/ipq5018.c +++ b/board/qca/arm/ipq5018/ipq5018.c @@ -23,6 +23,7 @@ #include DECLARE_GLOBAL_DATA_PTR; +extern int ipq_spi_init(u16); void uart1_configure_mux(void) { @@ -130,7 +131,14 @@ void reset_crashdump(void) void board_nand_init(void) { - return; +#ifdef CONFIG_QCA_SPI + int gpio_node; + gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio"); + if (gpio_node >= 0) { + qca_gpio_init(gpio_node); + ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX); + } +#endif } void enable_caches(void) diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 66172763e9..42828d39c7 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -36,6 +36,8 @@ ifdef CONFIG_QCA_SPI obj-$(CONFIG_ARCH_IPQ40xx) += qca_qup_spi_bam.o obj-$(CONFIG_ARCH_IPQ807x) += qca_qup_spi_bam.o obj-$(CONFIG_ARCH_IPQ6018) += qca_qup_spi_bam.o +obj-$(CONFIG_ARCH_IPQ5018) += qca_qup_spi_bam.o + obj-$(CONFIG_ARCH_IPQ806x) += ipq_spi.o endif obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o diff --git a/include/configs/ipq5018.h b/include/configs/ipq5018.h index 632054ef6b..522f1e9f86 100644 --- a/include/configs/ipq5018.h +++ b/include/configs/ipq5018.h @@ -30,7 +30,6 @@ #define CONFIG_SYS_BOOTM_LEN 0x1000000 #define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */ -#define CONFIG_ENV_IS_NOWHERE 1 /* *Size of malloc() pool @@ -129,7 +128,28 @@ extern loff_t board_env_size; #define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_SYS_NAND_ONFI_DETECTION +/* +* SPI Flash Configs +*/ +#define CONFIG_QCA_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED (48 * 1000 * 1000) +#define CONFIG_SPI_FLASH_BAR 1 +#define CONFIG_SPI_FLASH_USE_4K_SECTORS +#define CONFIG_IPQ_4B_ADDR_SWITCH_REQD +#define CONFIG_QUP_SPI_USE_DMA 0 +#define CONFIG_EFI_PARTITION +#define CONFIG_QCA_BAM 1 /* * Expose SPI driver as a pseudo NAND driver to make use * of U-Boot's MTD framework. @@ -147,7 +167,6 @@ extern loff_t board_env_size; #define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX #define QCA_SPI_NOR_DEVICE "spi0.0" -#define CONFIG_QUP_SPI_USE_DMA 1 /* * U-Boot Env Configs