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u-boot: drivers: net: Fix ppe tdm and sched config.

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Change-Id: Ib0eca1943f4e8a238a9e6326f21984c84f8a3f4d
Signed-off-by: speriaka <speriaka@codeaurora.org>
This commit is contained in:
speriaka 2019-05-24 21:21:37 +05:30
parent 68a334c872
commit 58f0bf4034
1 changed files with 148 additions and 658 deletions
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806
drivers/net/ipq6018/ipq6018_ppe.c
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@ -376,8 +376,6 @@ static void ipq6018_ppe_flow_map_tbl_set(int queue, int port)
*/
static void ipq6018_ppe_tdm_configuration(void)
{
int i = 0;
/*
* TDM is configured with instructions for each tick
* Port/action are configured as given below
@ -390,409 +388,104 @@ static void ipq6018_ppe_tdm_configuration(void)
* 5~6:Ethernet 5G
* 7~8:Security0/1
*/
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_QCOM1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_QCOM3);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_QCOM2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_QCOM4);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID
| IPQ6018_PPE_TDM_CFG_DIR_EGRESS
| IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_QCOM1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_QCOM3);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_QCOM2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_QCOM4);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_INGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10),
IPQ6018_PPE_TDM_CFG_VALID |
IPQ6018_PPE_TDM_CFG_DIR_EGRESS |
IPQ6018_PPE_PORT_CRYPTO1);
/* Set TDM Depth to 100 entries */
ipq6018_ppe_reg_write(IPQ6018_PPE_TDM_CFG_DEPTH_OFFSET, IPQ6018_PPE_TDM_CFG_DEPTH_VAL);
ipq6018_ppe_reg_write(0xc000, 0x20);
ipq6018_ppe_reg_write(0xc010, 0x30);
ipq6018_ppe_reg_write(0xc020, 0x25);
ipq6018_ppe_reg_write(0xc030, 0x34);
ipq6018_ppe_reg_write(0xc040, 0x21);
ipq6018_ppe_reg_write(0xc050, 0x35);
ipq6018_ppe_reg_write(0xc060, 0x26);
ipq6018_ppe_reg_write(0xc070, 0x36);
ipq6018_ppe_reg_write(0xc080, 0x20);
ipq6018_ppe_reg_write(0xc090, 0x30);
ipq6018_ppe_reg_write(0xc0a0, 0x27);
ipq6018_ppe_reg_write(0xc0b0, 0x37);
ipq6018_ppe_reg_write(0xc0c0, 0x24);
ipq6018_ppe_reg_write(0xc0d0, 0x30);
ipq6018_ppe_reg_write(0xc0e0, 0x26);
ipq6018_ppe_reg_write(0xc0f0, 0x35);
ipq6018_ppe_reg_write(0xc100, 0x20);
ipq6018_ppe_reg_write(0xc110, 0x30);
ipq6018_ppe_reg_write(0xc120, 0x22);
ipq6018_ppe_reg_write(0xc130, 0x36);
ipq6018_ppe_reg_write(0xc140, 0x27);
ipq6018_ppe_reg_write(0xc150, 0x37);
ipq6018_ppe_reg_write(0xc160, 0x25);
ipq6018_ppe_reg_write(0xc170, 0x35);
ipq6018_ppe_reg_write(0xc180, 0x20);
ipq6018_ppe_reg_write(0xc190, 0x30);
ipq6018_ppe_reg_write(0xc1a0, 0x26);
ipq6018_ppe_reg_write(0xc1b0, 0x36);
ipq6018_ppe_reg_write(0xc1c0, 0x27);
ipq6018_ppe_reg_write(0xc1d0, 0x33);
ipq6018_ppe_reg_write(0xc1e0, 0x25);
ipq6018_ppe_reg_write(0xc1f0, 0x37);
ipq6018_ppe_reg_write(0xc200, 0x20);
ipq6018_ppe_reg_write(0xc210, 0x30);
ipq6018_ppe_reg_write(0xc220, 0x26);
ipq6018_ppe_reg_write(0xc230, 0x35);
ipq6018_ppe_reg_write(0xc240, 0x20);
ipq6018_ppe_reg_write(0xc250, 0x36);
ipq6018_ppe_reg_write(0xc260, 0x27);
ipq6018_ppe_reg_write(0xc270, 0x37);
ipq6018_ppe_reg_write(0xc280, 0x20);
ipq6018_ppe_reg_write(0xc290, 0x30);
ipq6018_ppe_reg_write(0xc2a0, 0x25);
ipq6018_ppe_reg_write(0xc2b0, 0x34);
ipq6018_ppe_reg_write(0xc2c0, 0x26);
ipq6018_ppe_reg_write(0xc2d0, 0x36);
ipq6018_ppe_reg_write(0xc2e0, 0x27);
ipq6018_ppe_reg_write(0xc2f0, 0x37);
ipq6018_ppe_reg_write(0xc300, 0x20);
ipq6018_ppe_reg_write(0xc310, 0x30);
ipq6018_ppe_reg_write(0xc320, 0x24);
ipq6018_ppe_reg_write(0xc330, 0x35);
ipq6018_ppe_reg_write(0xc340, 0x25);
ipq6018_ppe_reg_write(0xc350, 0x31);
ipq6018_ppe_reg_write(0xc360, 0x26);
ipq6018_ppe_reg_write(0xc370, 0x36);
ipq6018_ppe_reg_write(0xc380, 0x20);
ipq6018_ppe_reg_write(0xc390, 0x30);
ipq6018_ppe_reg_write(0xc3a0, 0x27);
ipq6018_ppe_reg_write(0xc3b0, 0x37);
ipq6018_ppe_reg_write(0xc3c0, 0x20);
ipq6018_ppe_reg_write(0xc3d0, 0x34);
ipq6018_ppe_reg_write(0xc3e0, 0x25);
ipq6018_ppe_reg_write(0xc3f0, 0x36);
ipq6018_ppe_reg_write(0xc400, 0x20);
ipq6018_ppe_reg_write(0xc410, 0x30);
ipq6018_ppe_reg_write(0xc420, 0x26);
ipq6018_ppe_reg_write(0xc430, 0x32);
ipq6018_ppe_reg_write(0xc440, 0x27);
ipq6018_ppe_reg_write(0xc450, 0x37);
ipq6018_ppe_reg_write(0xc460, 0x25);
ipq6018_ppe_reg_write(0xc470, 0x35);
ipq6018_ppe_reg_write(0xc480, 0x20);
ipq6018_ppe_reg_write(0xc490, 0x30);
ipq6018_ppe_reg_write(0xc4a0, 0x26);
ipq6018_ppe_reg_write(0xc4b0, 0x36);
ipq6018_ppe_reg_write(0xc4c0, 0x23);
ipq6018_ppe_reg_write(0xc4d0, 0x37);
ipq6018_ppe_reg_write(0xc4e0, 0x27);
ipq6018_ppe_reg_write(0xc4f0, 0x35);
ipq6018_ppe_reg_write(0xc500, 0x20);
ipq6018_ppe_reg_write(0xc510, 0x30);
ipq6018_ppe_reg_write(0xc520, 0x25);
ipq6018_ppe_reg_write(0xc530, 0x36);
ipq6018_ppe_reg_write(0xc540, 0x26);
ipq6018_ppe_reg_write(0xc550, 0x30);
ipq6018_ppe_reg_write(0xc560, 0x27);
ipq6018_ppe_reg_write(0xc570, 0x37);
ipq6018_ppe_reg_write(0xc580, 0x20);
ipq6018_ppe_reg_write(0xc590, 0x30);
ipq6018_ppe_reg_write(0xc5a0, 0x24);
ipq6018_ppe_reg_write(0xc5b0, 0x35);
ipq6018_ppe_reg_write(0xc5c0, 0x26);
ipq6018_ppe_reg_write(0xc5d0, 0x36);
ipq6018_ppe_reg_write(0xc5e0, 0x27);
ipq6018_ppe_reg_write(0xc5f0, 0x37);
ipq6018_ppe_reg_write(0xb000, 0x80000060);
}
/*
@ -800,8 +493,6 @@ static void ipq6018_ppe_tdm_configuration(void)
*/
static void ipq6018_ppe_sched_configuration(void)
{
int i = 0;
/*
* PSCH_TDM_CFG_TBL_DES_PORT : determine which egress port traffic
* will be selected and transmitted out
@ -828,259 +519,58 @@ static void ipq6018_ppe_sched_configuration(void)
* IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
* IPQ6018_PPE_PORT_XGMAC2 | IPQ6018_PPE_PORT_EDMA);
*/
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_XGMAC1_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM3_BITPOS | IPQ6018_PPE_PORT_QCOM2_BITPOS |
IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_QCOM4 << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_QCOM4_BITPOS |
IPQ6018_PPE_PORT_QCOM3_BITPOS | IPQ6018_PPE_PORT_QCOM2_BITPOS |
IPQ6018_PPE_PORT_QCOM1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_CRYPTO1 << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_QCOM1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_QCOM1 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_QCOM2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_QCOM2 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_XGMAC1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_CRYPTO1 << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_QCOM3);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_QCOM3 << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_XGMAC1_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_QCOM4);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_QCOM4 << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_CRYPTO1 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM2_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_QCOM1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_QCOM1 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_QCOM2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_QCOM2 << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_XGMAC1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_CRYPTO1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_XGMAC2_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_CRYPTO1 << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_QCOM3);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC2 << 4) | IPQ6018_PPE_PORT_EDMA);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC2_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_QCOM3 << 4) | IPQ6018_PPE_PORT_XGMAC1);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_EDMA_BITPOS |
IPQ6018_PPE_PORT_QCOM4_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_EDMA << 4) | IPQ6018_PPE_PORT_XGMAC2);
ipq6018_ppe_reg_write(IPQ6018_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10),
((IPQ6018_PPE_PORT_CRYPTO1_BITPOS | IPQ6018_PPE_PORT_XGMAC1_BITPOS |
IPQ6018_PPE_PORT_EDMA_BITPOS | IPQ6018_PPE_PORT_QCOM3_BITPOS |
IPQ6018_PPE_PORT_QCOM2_BITPOS | IPQ6018_PPE_PORT_QCOM1_BITPOS) << 8) |
(IPQ6018_PPE_PORT_XGMAC1 << 4) | IPQ6018_PPE_PORT_QCOM4);
/* Set Sched Depth to 50 entries */
ipq6018_ppe_reg_write(IPQ6018_PPE_TDM_SCHED_DEPTH_OFFSET, IPQ6018_PPE_TDM_SCHED_DEPTH_VAL);
ipq6018_ppe_reg_write(0x47a000, 0xB706);
ipq6018_ppe_reg_write(0x47a010, 0xBE30);
ipq6018_ppe_reg_write(0x47a020, 0xDE65);
ipq6018_ppe_reg_write(0x47a030, 0xDD01);
ipq6018_ppe_reg_write(0x47a040, 0xBD56);
ipq6018_ppe_reg_write(0x47a050, 0xBE10);
ipq6018_ppe_reg_write(0x47a060, 0xEE64);
ipq6018_ppe_reg_write(0x47a070, 0xCF05);
ipq6018_ppe_reg_write(0x47a080, 0x9F46);
ipq6018_ppe_reg_write(0x47a090, 0xBE50);
ipq6018_ppe_reg_write(0x47a0a0, 0x7E67);
ipq6018_ppe_reg_write(0x47a0b0, 0x5F05);
ipq6018_ppe_reg_write(0x47a0c0, 0x9F76);
ipq6018_ppe_reg_write(0x47a0d0, 0xBE50);
ipq6018_ppe_reg_write(0x47a0e0, 0xFA62);
ipq6018_ppe_reg_write(0x47a0f0, 0xBB06);
ipq6018_ppe_reg_write(0x47a100, 0x9F25);
ipq6018_ppe_reg_write(0x47a110, 0xCF64);
ipq6018_ppe_reg_write(0x47a120, 0xEE50);
ipq6018_ppe_reg_write(0x47a130, 0xBE46);
ipq6018_ppe_reg_write(0x47a140, 0x3F07);
ipq6018_ppe_reg_write(0x47a150, 0x5F65);
ipq6018_ppe_reg_write(0x47a160, 0xDE70);
ipq6018_ppe_reg_write(0x47a170, 0xBE56);
ipq6018_ppe_reg_write(0x47a180, 0xB703);
ipq6018_ppe_reg_write(0x47a190, 0xE764);
ipq6018_ppe_reg_write(0x47a1a0, 0xEE30);
ipq6018_ppe_reg_write(0x47a1b0, 0xBE46);
ipq6018_ppe_reg_write(0x47a1c0, 0x9F05);
ipq6018_ppe_reg_write(0x47a1d0, 0xDD61);
ipq6018_ppe_reg_write(0x47a1e0, 0xFC50);
ipq6018_ppe_reg_write(0x47a1f0, 0xBE16);
ipq6018_ppe_reg_write(0x47a200, 0x9F05);
ipq6018_ppe_reg_write(0x47a210, 0x5F67);
ipq6018_ppe_reg_write(0x47a220, 0x7E50);
ipq6018_ppe_reg_write(0x47a230, 0xBE76);
ipq6018_ppe_reg_write(0x47a240, 0xAF04);
ipq6018_ppe_reg_write(0x47a250, 0xCF65);
ipq6018_ppe_reg_write(0x47a260, 0x9F46);
ipq6018_ppe_reg_write(0x47a270, 0xBE50);
ipq6018_ppe_reg_write(0x47a280, 0xFA62);
ipq6018_ppe_reg_write(0x47a290, 0xDB05);
ipq6018_ppe_reg_write(0x47a2a0, 0x9F26);
ipq6018_ppe_reg_write(0x47a2b0, 0xBE50);
ipq6018_ppe_reg_write(0x47a2c0, 0x7E67);
ipq6018_ppe_reg_write(0x47a2d0, 0x6F04);
ipq6018_ppe_reg_write(0x47a2e0, 0xAF76);
ipq6018_ppe_reg_write(0x47a2f0, 0x9F45);
ipq6018_ppe_reg_write(0x47a300, 0xDE60);
ipq6018_ppe_reg_write(0x47a310, 0xF653);
ipq6018_ppe_reg_write(0x400000, 0x32);
}
/*