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u-boot: drivers: Add ppe clk init for net driver

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Change-Id: Ica2db710d01b16b31997d96e383c3820149fcf68
Signed-off-by: speriaka <speriaka@codeaurora.org>
This commit is contained in:
speriaka 2019-05-24 10:04:00 +05:30
parent 68f0b47cfa
commit 68a334c872
1 changed files with 65 additions and 0 deletions
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65
board/qca/arm/ipq6018/ipq6018.c
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@ -972,11 +972,76 @@ void set_function_select_as_mdc_mdio(void)
}
}
static void ppe_clk_init(void)
{
uint32_t reg_val, i;
int gcc_ppeclock_base = 0x01868000;
int gcc_pll_base = 0x0009B780;
reg_val = readl(gcc_pll_base + 4);
reg_val=(reg_val&0xfffffff0)|0x7;
writel(reg_val, gcc_pll_base + 0x4);
reg_val = readl(gcc_pll_base);
reg_val=reg_val | 0x40;
writel(reg_val, gcc_pll_base);
mdelay(1);
reg_val=reg_val & (~0x40);
writel(reg_val, gcc_pll_base);
writel(0xbf, gcc_pll_base);
reg_val = readl(gcc_pll_base);
mdelay(1);
writel(0xff, gcc_pll_base);
reg_val = readl(gcc_pll_base);
mdelay(1);
/*set clock src and div*/
reg_val = 1 | (1 << 8);
writel(reg_val, gcc_ppeclock_base + 0x84);
/*issue command*/
reg_val = readl(gcc_ppeclock_base + 0x80);
reg_val |= 1;
writel(reg_val, gcc_ppeclock_base + 0x80);
mdelay(100);
reg_val = readl(gcc_ppeclock_base + 0x80);
reg_val |= 2;
writel(reg_val, gcc_ppeclock_base + 0x80);
/*set CBCR*/
for (i= 0; i < 4; i++) {
reg_val = readl(gcc_ppeclock_base + 0x190 + i*4);
reg_val |= 1;
writel(reg_val, gcc_ppeclock_base + 0x190 + i*4);
}
/*enable nss noc ppe*/
reg_val = readl(gcc_ppeclock_base + 0x300);
reg_val |= 1;
writel(reg_val, gcc_ppeclock_base + 0x300);
/*enable nss noc ppe config*/
reg_val = readl(gcc_ppeclock_base + 0x304);
reg_val |= 1;
writel(reg_val, gcc_ppeclock_base + 0x304);
/*enable crypto ppe*/
reg_val = readl(gcc_ppeclock_base + 0x310);
reg_val |= 1;
writel(reg_val, gcc_ppeclock_base + 0x310);
/*enable mac, ipe btq*/
for (i= 0; i < 8; i++) {
reg_val = readl(gcc_ppeclock_base + 0x320 + i*4);
reg_val |= 1;
writel(reg_val, gcc_ppeclock_base + 0x320 + i*4);
}
}
void eth_clock_enable(void)
{
/*
* ethernet clk rcgr block init
*/
ppe_clk_init();
writel(0x100, GCC_NSS_PORT1_RX_CFG_RCGR);
writel(0x1, GCC_NSS_PORT1_RX_CMD_RCGR);
writel(0x2, GCC_NSS_PORT1_RX_CMD_RCGR);