diff --git a/drivers/net/ipq9574/ipq9574_ppe.c b/drivers/net/ipq9574/ipq9574_ppe.c index 9a8b1f067a..16a0205898 100644 --- a/drivers/net/ipq9574/ipq9574_ppe.c +++ b/drivers/net/ipq9574/ipq9574_ppe.c @@ -19,19 +19,14 @@ #include #include #include "ipq9574_ppe.h" +#ifndef CONFIG_IPQ9574_RUMI #include "ipq9574_uniphy.h" +#endif #include #include "ipq_phy.h" DECLARE_GLOBAL_DATA_PTR; #define pr_info(fmt, args...) printf(fmt, ##args); -/* - * ipq9574_ppe_gpio_reg_write() - */ -static inline void ipq9574_ppe_gpio_reg_write(u32 reg, u32 val) -{ - writel(val, IPQ9574_PPE_FPGA_GPIO_BASE_ADDR + reg); -} /* * ipq9574_ppe_reg_read() @@ -127,6 +122,7 @@ static void ipq9574_ppe_vp_port_tbl_set(int port, int vsi) ipq9574_ppe_reg_write(addr, 0x0); ipq9574_ppe_reg_write(addr + 0x4 , 1 << 9 | vsi << 10); ipq9574_ppe_reg_write(addr + 0x8, 0x0); + ipq9574_ppe_reg_write(addr + 0xc, 0x0); } /* @@ -154,10 +150,10 @@ static void ipq9574_vsi_setup(int vsi, uint8_t group_mask) | group_mask); /* Set mask */ - ipq9574_ppe_reg_write(0x061800 + (vsi * 0x10), val); + ipq9574_ppe_reg_write(0x063800 + (vsi * 0x10), val); /* new addr lrn en | station move lrn en */ - ipq9574_ppe_reg_write(0x061804 + (vsi * 0x10), 0x9); + ipq9574_ppe_reg_write(0x063804 + (vsi * 0x10), 0x9); } /* @@ -170,6 +166,23 @@ static void ipq9574_gmac_port_enable(int port) ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x1); } +void ppe_port_bridge_txmac_set(int port_id, int status) +{ + uint32_t reg_value = 0; + + ipq9574_ppe_reg_read(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + (port_id * PORT_BRIDGE_CTRL_INC), ®_value); + if (status == 0) + reg_value |= TX_MAC_EN; + else + reg_value &= ~TX_MAC_EN; + + ipq9574_ppe_reg_write(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + + (port_id * PORT_BRIDGE_CTRL_INC), reg_value); + +} + +#ifndef CONFIG_IPQ9574_RUMI /* * ipq9574_port_mac_clock_reset() */ @@ -213,22 +226,22 @@ void ipq9574_speed_clock_set(int port, int speed_clock1, int speed_clock2) { /* gcc port first clock divider */ reg_value = 0; - reg_value = readl(GCC_NSS_PORT1_RX_CFG_RCGR + i*8 + port*0x10); + reg_value = readl(NSS_CC_PORT1_RX_CFG_RCGR + i*0xc + port*0x10); reg_value &= ~0x71f; reg_value |= speed_clock1; - writel(reg_value, GCC_NSS_PORT1_RX_CFG_RCGR + i*8 + port*0x10); + writel(reg_value, NSS_CC_PORT1_RX_CFG_RCGR + i*0xc + port*0x10); /* gcc port second clock divider */ reg_value = 0; - reg_value = readl(GCC_NSS_PORT1_RX_MISC + i*4 + port*0x10); + reg_value = readl(GCC_NSS_PORT1_RX_MISC + i*0xc + port*0x10); reg_value &= ~0xf; reg_value |= speed_clock2; - writel(reg_value, GCC_NSS_PORT1_RX_MISC + i*4 + port*0x10); + writel(reg_value, GCC_NSS_PORT1_RX_MISC + i*0xc + port*0x10); /* update above clock configuration */ reg_value = 0; - reg_value = readl(GCC_NSS_PORT1_RX_CMD_RCGR + i*8 + port*0x10); + reg_value = readl(NSS_CC_PORT1_RX_CMD_RCGR + i*0xc + port*0x10); reg_value &= ~0x1; reg_value |= 0x1; - writel(reg_value, GCC_NSS_PORT1_RX_CMD_RCGR + i*8 + port*0x10); + writel(reg_value, NSS_CC_PORT1_RX_CMD_RCGR + i*0xc + port*0x10); } } @@ -243,29 +256,6 @@ int phy_status_get_from_ppe(int port_id) return ((reg_field >> 7) & 0x1) ? 0 : 1; } -void ppe_port_bridge_txmac_set(int port_id, int status) -{ - uint32_t reg_value = 0; - - ipq9574_ppe_reg_read(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + - (port_id * PORT_BRIDGE_CTRL_INC), ®_value); - if (status == 0) - reg_value |= TX_MAC_EN; - else - reg_value &= ~TX_MAC_EN; - - ipq9574_ppe_reg_write(IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + - (port_id * PORT_BRIDGE_CTRL_INC), reg_value); - -} - -void ipq9574_pqsgmii_speed_set(int port, int speed, int status) -{ - ppe_port_bridge_txmac_set(port + 1, status); - ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_SPEED + (0x200 * port), speed); - ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_ENABLE + (0x200 * port), 0x73); -} - void ppe_xgmac_speed_set(uint32_t uniphy_index, int speed) { uint32_t reg_value = 0; @@ -380,6 +370,16 @@ void ipq9574_uxsgmii_speed_set(int port, int speed, int duplex, ppe_port_rxmac_status_set(uniphy_index - 1); ppe_mac_packet_filter_set(uniphy_index - 1); } +#endif + +void ipq9574_pqsgmii_speed_set(int port, int speed, int status) +{ + ppe_port_bridge_txmac_set(port + 1, status); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_SPEED + (0x200 * port), speed); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_ENABLE + (0x200 * port), 0x73); + ipq9574_ppe_reg_write(IPQ9574_PPE_MAC_MIB_CTL + (0x200 * port), 0x5); +} + /* * ipq9574_ppe_flow_port_map_tbl_port_num_set() */ @@ -410,423 +410,125 @@ static void ipq9574_ppe_flow_map_tbl_set(int queue, int port) */ static void ipq9574_ppe_tdm_configuration(void) { - int i = 0; - - /* - * TDM is configured with instructions for each tick - * Port/action are configured as given below - * - * 0x5:0x5 TDM_CFG_VALID 0:idle tick - * 0x4:0x4 TDM_CFG_DIR 0:ingress wr - * 1:egress rd - * 0x3:0x0 TDM_CFG_PORT_NUM 0:DMA - * 1~4:Ethernet 1G - * 5~6:Ethernet 5G - * 7~8:Security0/1 - */ - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_QTI1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_QTI3); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_QTI2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_QTI4); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID - | IPQ9574_PPE_TDM_CFG_DIR_EGRESS - | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_QTI1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_QTI3); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_QTI2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_QTI4); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_INGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_GPIO_OFFSET + (i++ * 0x10), - IPQ9574_PPE_TDM_CFG_VALID | - IPQ9574_PPE_TDM_CFG_DIR_EGRESS | - IPQ9574_PPE_PORT_CRYPTO1); - - /* Set TDM Depth to 100 entries */ - ipq9574_ppe_reg_write(IPQ9574_PPE_TDM_CFG_DEPTH_OFFSET, IPQ9574_PPE_TDM_CFG_DEPTH_VAL); + ipq9574_ppe_reg_write(0xc000, 0x26); + ipq9574_ppe_reg_write(0xc010, 0x34); + ipq9574_ppe_reg_write(0xc020, 0x25); + ipq9574_ppe_reg_write(0xc030, 0x30); + ipq9574_ppe_reg_write(0xc040, 0x21); + ipq9574_ppe_reg_write(0xc050, 0x36); + ipq9574_ppe_reg_write(0xc060, 0x20); + ipq9574_ppe_reg_write(0xc070, 0x35); + ipq9574_ppe_reg_write(0xc080, 0x26); + ipq9574_ppe_reg_write(0xc090, 0x31); + ipq9574_ppe_reg_write(0xc0a0, 0x22); + ipq9574_ppe_reg_write(0xc0b0, 0x36); + ipq9574_ppe_reg_write(0xc0c0, 0x27); + ipq9574_ppe_reg_write(0xc0d0, 0x30); + ipq9574_ppe_reg_write(0xc0e0, 0x25); + ipq9574_ppe_reg_write(0xc0f0, 0x32); + ipq9574_ppe_reg_write(0xc100, 0x26); + ipq9574_ppe_reg_write(0xc110, 0x36); + ipq9574_ppe_reg_write(0xc120, 0x20); + ipq9574_ppe_reg_write(0xc130, 0x37); + ipq9574_ppe_reg_write(0xc140, 0x24); + ipq9574_ppe_reg_write(0xc150, 0x30); + ipq9574_ppe_reg_write(0xc160, 0x23); + ipq9574_ppe_reg_write(0xc170, 0x36); + ipq9574_ppe_reg_write(0xc180, 0x26); + ipq9574_ppe_reg_write(0xc190, 0x34); + ipq9574_ppe_reg_write(0xc1a0, 0x25); + ipq9574_ppe_reg_write(0xc1b0, 0x33); + ipq9574_ppe_reg_write(0xc1c0, 0x20); + ipq9574_ppe_reg_write(0xc1d0, 0x36); + ipq9574_ppe_reg_write(0xc1e0, 0x21); + ipq9574_ppe_reg_write(0xc1f0, 0x35); + ipq9574_ppe_reg_write(0xc200, 0x26); + ipq9574_ppe_reg_write(0xc210, 0x30); + ipq9574_ppe_reg_write(0xc220, 0x27); + ipq9574_ppe_reg_write(0xc230, 0x31); + ipq9574_ppe_reg_write(0xc240, 0x20); + ipq9574_ppe_reg_write(0xc250, 0x36); + ipq9574_ppe_reg_write(0xc260, 0x25); + ipq9574_ppe_reg_write(0xc270, 0x37); + ipq9574_ppe_reg_write(0xc280, 0x26); + ipq9574_ppe_reg_write(0xc290, 0x30); + ipq9574_ppe_reg_write(0xc2a0, 0x22); + ipq9574_ppe_reg_write(0xc2b0, 0x35); + ipq9574_ppe_reg_write(0xc2c0, 0x20); + ipq9574_ppe_reg_write(0xc2d0, 0x36); + ipq9574_ppe_reg_write(0xc2e0, 0x23); + ipq9574_ppe_reg_write(0xc2f0, 0x32); + ipq9574_ppe_reg_write(0xc300, 0x26); + ipq9574_ppe_reg_write(0xc310, 0x30); + ipq9574_ppe_reg_write(0xc320, 0x25); + ipq9574_ppe_reg_write(0xc330, 0x33); + ipq9574_ppe_reg_write(0xc340, 0x20); + ipq9574_ppe_reg_write(0xc350, 0x36); + ipq9574_ppe_reg_write(0xc360, 0x27); + ipq9574_ppe_reg_write(0xc370, 0x35); + ipq9574_ppe_reg_write(0xc380, 0x26); + ipq9574_ppe_reg_write(0xc390, 0x30); + ipq9574_ppe_reg_write(0xc3a0, 0x24); + ipq9574_ppe_reg_write(0xc3b0, 0x37); + ipq9574_ppe_reg_write(0xc3c0, 0x20); + ipq9574_ppe_reg_write(0xc3d0, 0x36); + ipq9574_ppe_reg_write(0xc3e0, 0x25); + ipq9574_ppe_reg_write(0xc3f0, 0x34); + ipq9574_ppe_reg_write(0xc400, 0x26); + ipq9574_ppe_reg_write(0xc410, 0x30); + ipq9574_ppe_reg_write(0xc420, 0x21); + ipq9574_ppe_reg_write(0xc430, 0x35); + ipq9574_ppe_reg_write(0xc440, 0x20); + ipq9574_ppe_reg_write(0xc450, 0x36); + ipq9574_ppe_reg_write(0xc460, 0x22); + ipq9574_ppe_reg_write(0xc470, 0x31); + ipq9574_ppe_reg_write(0xc480, 0x26); + ipq9574_ppe_reg_write(0xc490, 0x30); + ipq9574_ppe_reg_write(0xc4a0, 0x25); + ipq9574_ppe_reg_write(0xc4b0, 0x32); + ipq9574_ppe_reg_write(0xc4c0, 0x20); + ipq9574_ppe_reg_write(0xc4d0, 0x36); + ipq9574_ppe_reg_write(0xc4e0, 0x27); + ipq9574_ppe_reg_write(0xc4f0, 0x35); + ipq9574_ppe_reg_write(0xc500, 0x26); + ipq9574_ppe_reg_write(0xc510, 0x30); + ipq9574_ppe_reg_write(0xc520, 0x23); + ipq9574_ppe_reg_write(0xc530, 0x37); + ipq9574_ppe_reg_write(0xc540, 0x20); + ipq9574_ppe_reg_write(0xc550, 0x36); + ipq9574_ppe_reg_write(0xc560, 0x25); + ipq9574_ppe_reg_write(0xc570, 0x33); + ipq9574_ppe_reg_write(0xc580, 0x26); + ipq9574_ppe_reg_write(0xc590, 0x30); + ipq9574_ppe_reg_write(0xc5a0, 0x24); + ipq9574_ppe_reg_write(0xc5b0, 0x35); + ipq9574_ppe_reg_write(0xc5c0, 0x20); + ipq9574_ppe_reg_write(0xc5d0, 0x36); + ipq9574_ppe_reg_write(0xc5e0, 0x21); + ipq9574_ppe_reg_write(0xc5f0, 0x34); + ipq9574_ppe_reg_write(0xc600, 0x26); + ipq9574_ppe_reg_write(0xc610, 0x30); + ipq9574_ppe_reg_write(0xc620, 0x25); + ipq9574_ppe_reg_write(0xc630, 0x31); + ipq9574_ppe_reg_write(0xc640, 0x20); + ipq9574_ppe_reg_write(0xc650, 0x36); + ipq9574_ppe_reg_write(0xc660, 0x22); + ipq9574_ppe_reg_write(0xc670, 0x35); + ipq9574_ppe_reg_write(0xc680, 0x26); + ipq9574_ppe_reg_write(0xc690, 0x30); + ipq9574_ppe_reg_write(0xc6a0, 0x23); + ipq9574_ppe_reg_write(0xc6b0, 0x32); + ipq9574_ppe_reg_write(0xc6c0, 0x20); + ipq9574_ppe_reg_write(0xc6d0, 0x36); + ipq9574_ppe_reg_write(0xc6e0, 0x25); + ipq9574_ppe_reg_write(0xc6f0, 0x33); + ipq9574_ppe_reg_write(0xc700, 0x26); + ipq9574_ppe_reg_write(0xc710, 0x30); + ipq9574_ppe_reg_write(0xc720, 0x24); + ipq9574_ppe_reg_write(0xc730, 0x35); + ipq9574_ppe_reg_write(0xc740, 0x20); + ipq9574_ppe_reg_write(0xc750, 0x36); + ipq9574_ppe_reg_write(0xb000, 0x80000076); } /* @@ -834,287 +536,66 @@ static void ipq9574_ppe_tdm_configuration(void) */ static void ipq9574_ppe_sched_configuration(void) { - int i = 0; - - /* - * PSCH_TDM_CFG_TBL_DES_PORT : determine which egress port traffic - * will be selected and transmitted out - * PSCH_TDM_CFG_TBL_ENS_PORT : determine which port’s queue need - * to be linked to scheduler at the current tick - * PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP : determine port bitmap - * for source of queue - * - * 0xf:0x8 PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP 1110_1110 - * (Port:765-432) - * - * 0x7:0x4 PSCH_TDM_CFG_TBL_ENS_PORT 0:DMA - * 1~4:Ethernet 1G - * 5~6:Ethernet 5G - * 7~8:Security0/1 - * - * 0x3:0x0 PSCH_TDM_CFG_TBL_DES_PORT 0:DMA - * 1~4:Ethernet 1G - * 5~6:Ethernet 5G - * 7~8:Security0/1 - * - * For eg, 0xee60 =((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - * IPQ9574_PPE_PORT_XGMAC1_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - * IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - * IPQ9574_PPE_PORT_XGMAC2 | IPQ9574_PPE_PORT_EDMA); - */ - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_XGMAC1_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI3_BITPOS | IPQ9574_PPE_PORT_QTI2_BITPOS | - IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_QTI4 << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_QTI4_BITPOS | - IPQ9574_PPE_PORT_QTI3_BITPOS | IPQ9574_PPE_PORT_QTI2_BITPOS | - IPQ9574_PPE_PORT_QTI1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_XGMAC2_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_EDMA_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_CRYPTO1 << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_QTI1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_QTI1 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_EDMA_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_QTI2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_EDMA_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_QTI2 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_XGMAC1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_XGMAC2_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_CRYPTO1 << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_QTI3); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_QTI3 << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_XGMAC1_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_QTI4); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_XGMAC2_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_QTI4 << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_XGMAC2_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_EDMA_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_CRYPTO1 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_EDMA_BITPOS | IPQ9574_PPE_PORT_QTI2_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_QTI1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_QTI1 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_EDMA_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_QTI2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_XGMAC2_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_QTI2 << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_XGMAC1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_CRYPTO1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_XGMAC2_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_CRYPTO1 << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_QTI3); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC2 << 4) | IPQ9574_PPE_PORT_EDMA); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC2_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_QTI3 << 4) | IPQ9574_PPE_PORT_XGMAC1); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_EDMA_BITPOS | - IPQ9574_PPE_PORT_QTI4_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_EDMA << 4) | IPQ9574_PPE_PORT_XGMAC2); - ipq9574_ppe_reg_write(IPQ9574_PPE_FPGA_SCHED_OFFSET + (i++ * 0x10), - ((IPQ9574_PPE_PORT_CRYPTO1_BITPOS | IPQ9574_PPE_PORT_XGMAC1_BITPOS | - IPQ9574_PPE_PORT_EDMA_BITPOS | IPQ9574_PPE_PORT_QTI3_BITPOS | - IPQ9574_PPE_PORT_QTI2_BITPOS | IPQ9574_PPE_PORT_QTI1_BITPOS) << 8) | - (IPQ9574_PPE_PORT_XGMAC1 << 4) | IPQ9574_PPE_PORT_QTI4); - - /* Set Sched Depth to 50 entries */ - ipq9574_ppe_reg_write(IPQ9574_PPE_TDM_SCHED_DEPTH_OFFSET, IPQ9574_PPE_TDM_SCHED_DEPTH_VAL); + ipq9574_ppe_reg_write(0x0047a000, 0xCF65); + ipq9574_ppe_reg_write(0x0047a010, 0x9F76); + ipq9574_ppe_reg_write(0x0047a020, 0x3F17); + ipq9574_ppe_reg_write(0x0047a030, 0x3F56); + ipq9574_ppe_reg_write(0x0047a040, 0xBD01); + ipq9574_ppe_reg_write(0x0047a050, 0xDD65); + ipq9574_ppe_reg_write(0x0047a060, 0xDE20); + ipq9574_ppe_reg_write(0x0047a070, 0xDE65); + ipq9574_ppe_reg_write(0x0047a080, 0x9F06); + ipq9574_ppe_reg_write(0x0047a090, 0xBB52); + ipq9574_ppe_reg_write(0x0047a0a0, 0xFA60); + ipq9574_ppe_reg_write(0x0047a0b0, 0xBE56); + ipq9574_ppe_reg_write(0x0047a0c0, 0x9F05); + ipq9574_ppe_reg_write(0x0047a0d0, 0xDE60); + ipq9574_ppe_reg_write(0x0047a0e0, 0x7E57); + ipq9574_ppe_reg_write(0x0047a0f0, 0x5F65); + ipq9574_ppe_reg_write(0x0047a100, 0x9F76); + ipq9574_ppe_reg_write(0x0047a110, 0xBE30); + ipq9574_ppe_reg_write(0x0047a120, 0xBE56); + ipq9574_ppe_reg_write(0x0047a130, 0xB703); + ipq9574_ppe_reg_write(0x0047a140, 0xD765); + ipq9574_ppe_reg_write(0x0047a150, 0xDE40); + ipq9574_ppe_reg_write(0x0047a160, 0xDE65); + ipq9574_ppe_reg_write(0x0047a170, 0x9F06); + ipq9574_ppe_reg_write(0x0047a180, 0xAF54); + ipq9574_ppe_reg_write(0x0047a190, 0xEE60); + ipq9574_ppe_reg_write(0x0047a1a0, 0xBE16); + ipq9574_ppe_reg_write(0x0047a1b0, 0x9F25); + ipq9574_ppe_reg_write(0x0047a1c0, 0xDE60); + ipq9574_ppe_reg_write(0x0047a1d0, 0x7E57); + ipq9574_ppe_reg_write(0x0047a1e0, 0x5F05); + ipq9574_ppe_reg_write(0x0047a1f0, 0x9F36); + ipq9574_ppe_reg_write(0x0047a200, 0xBE50); + ipq9574_ppe_reg_write(0x0047a210, 0xBE76); + ipq9574_ppe_reg_write(0x0047a220, 0xBD01); + ipq9574_ppe_reg_write(0x0047a230, 0xDD65); + ipq9574_ppe_reg_write(0x0047a240, 0x9F06); + ipq9574_ppe_reg_write(0x0047a250, 0x9F75); + ipq9574_ppe_reg_write(0x0047a260, 0xDE60); + ipq9574_ppe_reg_write(0x0047a270, 0xFA52); + ipq9574_ppe_reg_write(0x0047a280, 0xDB05); + ipq9574_ppe_reg_write(0x0047a290, 0x9F76); + ipq9574_ppe_reg_write(0x0047a2a0, 0x9F05); + ipq9574_ppe_reg_write(0x0047a2b0, 0x9F16); + ipq9574_ppe_reg_write(0x0047a2c0, 0xBE50); + ipq9574_ppe_reg_write(0x0047a2d0, 0xDE65); + ipq9574_ppe_reg_write(0x0047a2e0, 0x9F06); + ipq9574_ppe_reg_write(0x0047a2f0, 0x9F25); + ipq9574_ppe_reg_write(0x0047a300, 0x9F06); + ipq9574_ppe_reg_write(0x0047a310, 0xBE50); + ipq9574_ppe_reg_write(0x0047a320, 0xBE65); + ipq9574_ppe_reg_write(0x0047a330, 0x9F36); + ipq9574_ppe_reg_write(0x0047a340, 0x9F05); + ipq9574_ppe_reg_write(0x0047a350, 0x9F46); + ipq9574_ppe_reg_write(0x0047a360, 0xBE50); + ipq9574_ppe_reg_write(0x0047a370, 0x7E67); + ipq9574_ppe_reg_write(0x0047a380, 0x7753); + ipq9574_ppe_reg_write(0x0047a390, 0xF660); + ipq9574_ppe_reg_write(0x0047a3a0, 0xEE54); + ipq9574_ppe_reg_write(0x00400000, 0x3b); } /* @@ -1137,52 +618,69 @@ static void ipq9574_ppe_e_sp_cfg_tbl_drr_id_set(int id) static void ppe_port_mux_set(int port_id, int port_type, int mode) { + uint32_t mux_mac_type = 0; union port_mux_ctrl_u port_mux_ctrl; int nodeoff; + printf("\nport id is: %d, port type is %d, mode is %d", + port_id, port_type, mode); nodeoff = fdt_path_offset(gd->fdt_blob, "/ess-switch"); - ipq9574_ppe_reg_read(IPQ9574_PORT_MUX_CTRL, &(port_mux_ctrl.val)); + if (port_type == PORT_GMAC_TYPE) + mux_mac_type = IPQ9574_PORT_MUX_MAC_TYPE; + else if (port_type == PORT_XGMAC_TYPE) + mux_mac_type = IPQ9574_PORT_MUX_XMAC_TYPE; + else + printf("\nAttention!!!..Port type configured wrongly..port_id = %d, mode = %d, port_type = %d", + port_id, mode, port_type); + + port_mux_ctrl.val = 0; + ipq9574_ppe_reg_read(IPQ9574_PORT_MUX_CTRL, &(port_mux_ctrl.val)); + printf("\nBEFORE UPDATE: Port MUX CTRL value is %u", port_mux_ctrl.val); + switch (port_id) { - case 3: - case 4: - if (mode == PORT_WRAPPER_SGMII_PLUS || mode == PORT_WRAPPER_SGMII0_RGMII4) { - port_mux_ctrl.bf.port3_pcs_sel = CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; - port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS; - port_mux_ctrl.bf.pcs0_ch0_sel = CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS; - port_mux_ctrl.bf.pcs0_ch4_sel = CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK; - } else if (mode == PORT_WRAPPER_PSGMII || mode == PORT_WRAPPER_QSGMII) { - if (fdtdec_get_int(gd->fdt_blob, nodeoff, "malibu2port_phy", 0)) { - port_mux_ctrl.bf.port3_pcs_sel = CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4; - port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; - port_mux_ctrl.bf.pcs0_ch4_sel = CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK; - } else { - port_mux_ctrl.bf.port3_pcs_sel = CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; - port_mux_ctrl.bf.port4_pcs_sel = CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; - port_mux_ctrl.bf.pcs0_ch0_sel = CPPE_PCS0_CHANNEL0_SEL_PSGMII; - port_mux_ctrl.bf.pcs0_ch4_sel = CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK; - } - } + case PORT1: + port_mux_ctrl.bf.port1_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port1_pcs_sel = 0; break; - case 5: - if (mode == PORT_WRAPPER_SGMII_PLUS || mode == PORT_WRAPPER_SGMII0_RGMII4 || - mode == PORT_WRAPPER_SGMII_FIBER) { - port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0; - port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_GMAC; - } else if (mode == PORT_WRAPPER_PSGMII) { - port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4; - port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_GMAC; - } else if (mode == PORT_WRAPPER_USXGMII || mode == PORT_WRAPPER_10GBASE_R) { - port_mux_ctrl.bf.port5_pcs_sel = CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0; - port_mux_ctrl.bf.port5_gmac_sel = CPPE_PORT5_GMAC_SEL_XGMAC; - } + case PORT2: + port_mux_ctrl.bf.port2_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port2_pcs_sel = 0; + break; + case PORT3: + port_mux_ctrl.bf.port3_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port3_pcs_sel = 0; + break; + case PORT4: + port_mux_ctrl.bf.port4_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port4_pcs_sel = 0; + break; + case PORT5: + port_mux_ctrl.bf.port5_mac_sel = mux_mac_type; + /* + * uniphy0_port5 = <1> should be added in DT if port5 + * is part of uniphy 0, otherwise it will be assumed + * to be part of uniphy1. + */ + if (fdtdec_get_int(gd->fdt_blob, nodeoff, + "uniphy0_port5", 0)) + port_mux_ctrl.bf.port5_pcs_sel = + IPQ9574_PORT5_MUX_PCS_UNIPHY0; + else + port_mux_ctrl.bf.port5_pcs_sel = + IPQ9574_PORT5_MUX_PCS_UNIPHY1; + break; + case PORT6: + port_mux_ctrl.bf.port6_mac_sel = mux_mac_type; + port_mux_ctrl.bf.port6_pcs_sel = 0; break; default: break; } - ipq9574_ppe_reg_write(IPQ9574_PORT_MUX_CTRL, port_mux_ctrl.val); + ipq9574_ppe_reg_write(IPQ9574_PORT_MUX_CTRL, port_mux_ctrl.val); + printf("\nAFTER UPDATE: Port MUX CTRL value is %u", port_mux_ctrl.val); } void ppe_port_mux_mac_type_set(int port_id, int mode) @@ -1191,52 +689,75 @@ void ppe_port_mux_mac_type_set(int port_id, int mode) switch(mode) { - case PORT_WRAPPER_PSGMII: - case PORT_WRAPPER_SGMII0_RGMII4: - case PORT_WRAPPER_SGMII_PLUS: - case PORT_WRAPPER_SGMII_FIBER: + case EPORT_WRAPPER_PSGMII: + case EPORT_WRAPPER_SGMII0_RGMII4: + case EPORT_WRAPPER_SGMII_PLUS: + case EPORT_WRAPPER_SGMII_FIBER: port_type = PORT_GMAC_TYPE; break; - case PORT_WRAPPER_USXGMII: - case PORT_WRAPPER_10GBASE_R: + case EPORT_WRAPPER_USXGMII: + case EPORT_WRAPPER_10GBASE_R: port_type = PORT_XGMAC_TYPE; break; default: + printf("\nError during port_type set: mode is %d, port_id is: %d", + mode, port_id); return; } ppe_port_mux_set(port_id, port_type, mode); } - - void ipq9574_ppe_interface_mode_init(void) { - uint32_t mode0, mode1; + uint32_t mode0, mode1, mode2; int node; - node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); if (node < 0) { - printf("Error: ess-switch not specified in dts"); + printf("\nError: ess-switch not specified in dts"); return; } - mode0 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode", -1); + mode0 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1); if (mode0 < 0) { - printf("Error: switch_mac_mode not specified in dts"); + printf("\nError: switch_mac_mode0 not specified in dts"); return; } mode1 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1); if (mode1 < 0) { - printf("Error: switch_mac_mode1 not specified in dts"); + printf("\nError: switch_mac_mode1 not specified in dts"); return; } + mode2 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode2", -1); + if (mode1 < 0) { + printf("\nError: switch_mac_mode2 not specified in dts"); + return; + } + +#ifndef CONFIG_IPQ9574_RUMI ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0); ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1); + ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE2, mode2); +#endif - ppe_port_mux_mac_type_set(4, mode0); - ppe_port_mux_mac_type_set(5, mode1); + /* + * uniphy0_port5 = <1> should be added in DT if port5 + * is part of uniphy 0, otherwise it will be assumed + * to be part of uniphy1. + * + * Port 1-4 are used mac type as GMAC by default but + * Port5 and Port6 can be used as GMAC or XGMAC. + */ + ppe_port_mux_mac_type_set(PORT1, mode0); + ppe_port_mux_mac_type_set(PORT2, mode0); + ppe_port_mux_mac_type_set(PORT3, mode0); + ppe_port_mux_mac_type_set(PORT4, mode0); + if (fdtdec_get_int(gd->fdt_blob, node, "uniphy0_port5", 0)) + ppe_port_mux_mac_type_set(PORT5, mode0); + else + ppe_port_mux_mac_type_set(PORT5, mode1); + ppe_port_mux_mac_type_set(PORT6, mode2); } /* @@ -1251,12 +772,6 @@ void ipq9574_ppe_provision_init(void) ipq9574_ppe_tdm_configuration(); ipq9574_ppe_sched_configuration(); - /* disable clock gating */ - ipq9574_ppe_reg_write(0x000008, 0x0); - - /* flow ctrl disable */ - ipq9574_ppe_reg_write(0x200368, 0xc88); - #ifdef CONFIG_IPQ9574_BRIDGED_MODE /* Add CPU port 0 to VSI 2 */ ipq9574_ppe_vp_port_tbl_set(0, 2); @@ -1267,6 +782,7 @@ void ipq9574_ppe_provision_init(void) ipq9574_ppe_vp_port_tbl_set(3, 2); ipq9574_ppe_vp_port_tbl_set(4, 2); ipq9574_ppe_vp_port_tbl_set(5, 2); + ipq9574_ppe_vp_port_tbl_set(6, 2); #else ipq9574_ppe_vp_port_tbl_set(1, 2); @@ -1292,6 +808,10 @@ void ipq9574_ppe_provision_init(void) ipq9574_ppe_e_sp_cfg_tbl_drr_id_set(i); } + /* sp_cfg_l0 and sp_cfg_l1 configuration */ + ipq9574_ppe_reg_write(IPQ9574_PPE_TM_SHP_CFG_L0, 0x12b); + ipq9574_ppe_reg_write(IPQ9574_PPE_TM_SHP_CFG_L1, 0x3f); + /* Port0 multicast queue */ ipq9574_ppe_reg_write(0x409000, 0x00000000); ipq9574_ppe_reg_write(0x403000, 0x00401000); @@ -1324,7 +844,7 @@ void ipq9574_ppe_provision_init(void) ipq9574_ppe_reg_write(0x060038, 0xc0); #ifdef CONFIG_IPQ9574_BRIDGED_MODE - ipq9574_vsi_setup(2, 0x3f); + ipq9574_vsi_setup(2, 0x7f); #else ipq9574_vsi_setup(2, 0x03); ipq9574_vsi_setup(3, 0x05); @@ -1337,8 +857,8 @@ void ipq9574_ppe_provision_init(void) ipq9574_ppe_reg_write(IPQ9574_PPE_STP_BASE + (0x4 * i), 0x3); ipq9574_ppe_interface_mode_init(); - /* Port 0-4 disable */ - for (i = 0; i < 5; i++) { + /* Port 0-5 disable */ + for (i = 0; i < 6; i++) { ipq9574_gmac_port_enable(i); ppe_port_bridge_txmac_set(i + 1, 1); } diff --git a/drivers/net/ipq9574/ipq9574_ppe.h b/drivers/net/ipq9574/ipq9574_ppe.h index 63063bdc4e..40b4f8772b 100644 --- a/drivers/net/ipq9574/ipq9574_ppe.h +++ b/drivers/net/ipq9574/ipq9574_ppe.h @@ -25,26 +25,44 @@ #include #include -#define GCC_NSS_PORT1_RX_CMD_RCGR 0x01868020 -#define GCC_NSS_PORT1_RX_CFG_RCGR 0x01868024 +#define NSS_CC_PORT1_RX_CMD_RCGR 0x39B28110 +#define NSS_CC_PORT1_RX_CFG_RCGR 0x39B28114 #define GCC_NSS_PORT1_RX_MISC 0x01868400 #define IPQ9574_PPE_BASE_ADDR 0x3a000000 #define IPQ9574_PPE_REG_SIZE 0x1000000 +#define PORT1 1 +#define PORT2 2 +#define PORT3 3 #define PORT4 4 #define PORT5 5 +#define PORT6 6 + +#define IPQ9574_PORT5_MUX_PCS_UNIPHY0 0x0 +#define IPQ9574_PORT5_MUX_PCS_UNIPHY1 0x1 + #define PORT_GMAC_TYPE 1 #define PORT_XGMAC_TYPE 2 +#define IPQ9574_PORT_MUX_MAC_TYPE 0 +#define IPQ9574_PORT_MUX_XMAC_TYPE 1 + struct port_mux_ctrl { - uint32_t port3_pcs_sel:2; - uint32_t port4_pcs_sel:2; - uint32_t port5_pcs_sel:2; - uint32_t port5_gmac_sel:1; - uint32_t pcs0_ch4_sel:1; - uint32_t pcs0_ch0_sel:1; - uint32_t _reserved0:23; + uint32_t port1_pcs_sel:1; + uint32_t port2_pcs_sel:1; + uint32_t port3_pcs_sel:1; + uint32_t port4_pcs_sel:1; + uint32_t port5_pcs_sel:1; + uint32_t port6_pcs_sel:1; + uint32_t _reserved0:2; + uint32_t port1_mac_sel:1; + uint32_t port2_mac_sel:1; + uint32_t port3_mac_sel:1; + uint32_t port4_mac_sel:1; + uint32_t port5_mac_sel:1; + uint32_t port6_mac_sel:1; + uint32_t _reserved1:18; }; union port_mux_ctrl_u { @@ -108,25 +126,15 @@ union ipo_action_u { }; #define IPQ9574_PORT_MUX_CTRL 0x10 -#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2 0 -#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4 1 -#define CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3 0 -#define CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS 1 -#define CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4 0 -#define CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0 1 -#define CPPE_PORT5_GMAC_SEL_GMAC 0 -#define CPPE_PORT5_GMAC_SEL_XGMAC 1 -#define CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK 0x0 -#define CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK 0x1 -#define CPPE_PCS0_CHANNEL0_SEL_PSGMII 0x0 -#define CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS 0x1 -#define CPPE_DETECTION_PHY_FAILURE 0xFFFF +#define IPQ9574_PORT_MUX_CTRL_NUM 1 +#define IPQ9574_PORT_MUX_CTRL_INC 0x4 +#define IPQ9574_PORT_MUX_CTRL_DEFAULT 0x0 #define PORT_PHY_STATUS_ADDRESS 0x44 #define PORT_PHY_STATUS_PORT5_1_OFFSET 16 #define IPQ9574_PPE_IPE_L3_BASE_ADDR 0x200000 -#define IPQ9574_PPE_L3_VP_PORT_TBL_ADDR (IPQ9574_PPE_IPE_L3_BASE_ADDR + 0x1000) +#define IPQ9574_PPE_L3_VP_PORT_TBL_ADDR (IPQ9574_PPE_IPE_L3_BASE_ADDR + 0x4000) #define IPQ9574_PPE_L3_VP_PORT_TBL_INC 0x10 #define IPQ9574_PPE_QUEUE_MANAGER_BASE_ADDR 0x800000 @@ -144,8 +152,14 @@ union ipo_action_u { #define IPQ9574_PPE_MAC_MIB_CTL 0x001034 #define IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR 0x400000 +#define IPQ9574_PPE_TM_SHP_CFG_L0_OFFSET 0x00000030 +#define IPQ9574_PPE_TM_SHP_CFG_L1_OFFSET 0x00000034 +#define IPQ9574_PPE_TM_SHP_CFG_L0 IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_TM_SHP_CFG_L0_OFFSET +#define IPQ9574_PPE_TM_SHP_CFG_L1 IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ + IPQ9574_PPE_TM_SHP_CFG_L1_OFFSET -#define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x8000 +#define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x10000 #define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10 #define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\ IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_ADDR) @@ -219,7 +233,7 @@ union ipo_action_u { #define IPQ9574_PPE_PORT_XGMAC2_BITPOS (1 << IPQ9574_PPE_PORT_XGMAC2) #define IPQ9574_PPE_PORT_CRYPTO1_BITPOS (1 << IPQ9574_PPE_PORT_CRYPTO1) -#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x3000 +#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x500000 #define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION 0x4000 #define USS (1 << 31) #define SS(i) (i << 29) diff --git a/drivers/net/ipq_common/ipq_phy.h b/drivers/net/ipq_common/ipq_phy.h index 1ff35cd196..1e7e689e87 100755 --- a/drivers/net/ipq_common/ipq_phy.h +++ b/drivers/net/ipq_common/ipq_phy.h @@ -18,7 +18,7 @@ #include #define PHY_MAX 6 -#define IPQ9574_PHY_MAX 5 +#define IPQ9574_PHY_MAX 6 #define IPQ6018_PHY_MAX 5 #define MDIO_CTRL_0_REG 0x00090040 #define MDIO_CTRL_0_DIV(x) (x << 0) @@ -88,6 +88,31 @@ typedef enum { FAL_CABLE_STATUS_BUTT = 0xffff, } fal_cable_status_t; +enum eport_wrapper_cfg { + EPORT_WRAPPER_PSGMII = 0, + EPORT_WRAPPER_PSGMII_RGMII5, + EPORT_WRAPPER_SGMII0_RGMII5, + EPORT_WRAPPER_SGMII1_RGMII5, + EPORT_WRAPPER_PSGMII_RMII0, + EPORT_WRAPPER_PSGMII_RMII1, + EPORT_WRAPPER_PSGMII_RMII0_RMII1, + EPORT_WRAPPER_PSGMII_RGMII4, + EPORT_WRAPPER_SGMII0_RGMII4, + EPORT_WRAPPER_SGMII1_RGMII4, + EPORT_WRAPPER_SGMII4_RGMII4, + EPORT_WRAPPER_QSGMII, + EPORT_WRAPPER_SGMII_PLUS, + EPORT_WRAPPER_USXGMII, + EPORT_WRAPPER_10GBASE_R, + EPORT_WRAPPER_SGMII_CHANNEL0, + EPORT_WRAPPER_SGMII_CHANNEL1, + EPORT_WRAPPER_SGMII_CHANNEL4, + EPORT_WRAPPER_RGMII, + EPORT_WRAPPER_PSGMII_FIBER, + EPORT_WRAPPER_SGMII_FIBER, + EPORT_WRAPPER_MAX = 0xFF +}; + enum port_wrapper_cfg { PORT_WRAPPER_PSGMII = 0, PORT_WRAPPER_SGMII0_RGMII4,