From 4a2716fc06ae60baada5438e9062fff08e708a46 Mon Sep 17 00:00:00 2001 From: Praveenkumar I Date: Fri, 24 Feb 2023 10:05:00 +0530 Subject: [PATCH] pci: ipq9574: Fix PCIe single lane PHY configuration Change-Id: Ie4f6f92a1cdb91b4cd97ec6ff1a80cef5780f162 Signed-off-by: Praveenkumar I --- drivers/pci/pci_ipq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci_ipq.c b/drivers/pci/pci_ipq.c index 6f127b0582..4115a35a62 100644 --- a/drivers/pci/pci_ipq.c +++ b/drivers/pci/pci_ipq.c @@ -670,7 +670,7 @@ static const struct phy_regs pcie_phy_v2_x2_init_seq_ipq[] = { }; static const struct phy_regs pcie_phy_v2_init_seq_ipq[] = { -#if !defined(CONFIG_IPQ6018) +#if defined(CONFIG_IPQ807x) { PCS_COM_POWER_DOWN_CONTROL, 0x00000001}, { PCIE_0_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x00000018}, { PCIE_0_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x00000001}, @@ -928,7 +928,7 @@ static const struct phy_regs pcie_phy_v2_init_seq_ipq[] = { { PCIE_0_PCS_COM_SW_RESET, 0x00000000}, { PCIE_0_PCS_COM_START_CONTROL, 0x00000002}, { PCIE_0_PCS_COM_START_CONTROL, 0x00000003}, -#else +#elif defined(CONFIG_IPQ6018) { PCIE_0_PCS_COM_POWER_DOWN_CONTROL, 0x03 }, { PCIE_0_QSERDES_PLL_SSC_PER1, 0x7D }, { PCIE_0_QSERDES_PLL_SSC_PER2, 0x01 },