From 441cf444f82ce2ef64aeaa2b10c88f4e3fc5e8ae Mon Sep 17 00:00:00 2001 From: sameeruddin shaik Date: Fri, 8 Mar 2019 10:41:36 +0530 Subject: [PATCH] ipq40xx: make sure that the cache flush instruction gets complete Adding the DSB/ISB instructions in the dcache flush functions to make sure that the cache flush instruction gets completed before another instruction executes. Change-Id: I0bc2222cb040a96cc7413586b9131904bd5d1167 Signed-off-by: sameeruddin shaik --- arch/arm/cpu/armv7/cache_v7.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index c4f673f917..9e930511c9 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -118,6 +118,8 @@ static void v7_inval_dcache_level_setway(void) } /* DSB to make sure the operation is complete */ DSB; + /* Full system ISB - make sure the instruction stream sees it */ + ISB; } static void v7_clean_inval_dcache_level_setway(void) @@ -142,6 +144,8 @@ static void v7_clean_inval_dcache_level_setway(void) } /* DSB to make sure the operation is complete */ DSB; + /* Full system ISB - make sure the instruction stream sees it */ + ISB; } static void v7_maint_dcache_level_setway(void) @@ -173,6 +177,8 @@ static void v7_maint_dcache_level_setway(void) } else if (c1.operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) { v7_clean_inval_dcache_level_setway(); } + DSB; + ISB; } static void v7_maint_dcache_all(void) @@ -188,6 +194,8 @@ static void v7_maint_dcache_all(void) v7_maint_dcache_level_setway(); c1.level_start_bit += 3; } + DSB; + ISB; } static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len) @@ -259,6 +267,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) /* DSB to make sure the operation is complete */ DSB; + /* Full system ISB - make sure the instruction stream sees it */ + ISB; } /* Invalidate TLB */