mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
qca: ipq6018: Adding support for IPQ6018
Added config, dts and initial board support code for ipq6018 Change-Id: I8cdc6d43f936179733c2c27e2b52dcf3477a892e Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
This commit is contained in:
Rajkumar Ayyasamy
Antony Arun T
parent
3fc81744c3
commit
377c85ed8d
16 changed files with 946 additions and 5 deletions
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@ -445,6 +445,14 @@ config ARCH_IPQ807x
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select SYS_GENERIC_BOARD
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select QCA_COMMON
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config ARCH_IPQ6018
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bool "QCA, IPQ6018"
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select DM
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select DM_SERIAL
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select CPU_V7
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select SYS_GENERIC_BOARD
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select QCA_COMMON
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config ARCH_S5PC1XX
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bool "Samsung S5PC1XX"
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select CPU_V7
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@ -833,6 +841,7 @@ source "board/h2200/Kconfig"
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source "board/hisilicon/hikey/Kconfig"
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source "board/imx31_phycore/Kconfig"
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source "board/ipq40xx/Kconfig"
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source "board/ipq6018/Kconfig"
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source "board/ipq806x/Kconfig"
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source "board/ipq807x/Kconfig"
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source "board/isee/igep0033/Kconfig"
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@ -57,6 +57,8 @@ dtb-$(CONFIG_ARCH_IPQ40xx) += ipq40xx-dk01-c1.dtb \
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ipq40xx-dk01-s1.dtb \
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ipq40xx-dk06-c1.dtb
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dtb-$(CONFIG_ARCH_IPQ6018) += ipq6018-cp01.dtb \
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dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rk3288-firefly.dtb \
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rk3288-jerry.dtb \
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25
arch/arm/dts/ipq6018-cp01.dts
Normal file
25
arch/arm/dts/ipq6018-cp01.dts
Normal file
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@ -0,0 +1,25 @@
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/*
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "ipq6018-soc.dtsi"
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/ {
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model ="QCA, IPQ6018-CP01";
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compatible = "qca,ipq6018", "qca,ipq6018-cp01";
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machid = <0x08010000>;
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aliases {
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console = "/serial@78B3000";
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};
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};
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56
arch/arm/dts/ipq6018-soc.dtsi
Normal file
56
arch/arm/dts/ipq6018-soc.dtsi
Normal file
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@ -0,0 +1,56 @@
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/*
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/qcom/gpio-ipq6018.h>
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/ {
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serial@78B3000 {
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compatible = "qca,ipq-uartdm";
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reg = <0x78B3000 0x200>;
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id = <4>;
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bit_rate = <0xee>;
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serial_gpio {
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gpio1 {
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gpio = <23>;
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func = <2>;
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pull = <GPIO_NO_PULL>;
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oe = <GPIO_OE_ENABLE>;
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};
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gpio2 {
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gpio = <24>;
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func = <2>;
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pull = <GPIO_NO_PULL>;
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oe = <GPIO_OE_ENABLE>;
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};
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};
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};
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serial@78b0000 {
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compatible = "qca,ipq-uartdm";
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reg = <0x78b0000 0x200>;
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id = <2>;
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bit_rate = <0xff>;
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};
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timer {
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gcnt_base = <0x4a1000>;
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gcnt_cntcv_lo = <0x4a2000>;
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gcnt_cntcv_hi = <0x4a2004>;
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gpt_freq_hz = <48000000>;
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timer_load_val = <0x00FFFFFF 0xFFFFFFFF>;
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};
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};
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@ -1,7 +1,7 @@
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/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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* Copyright (c) 2009-2017 The Linux Foundation. All rights reserved.
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* Copyright (c) 2009-2018 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -30,7 +30,7 @@
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#ifndef __QPIC_NAND_H
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#define __QPIC_NAND_H
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#if defined(CONFIG_IPQ40XX) || defined(CONFIG_IPQ_RUMI)
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#if defined(CONFIG_IPQ40XX) || defined(CONFIG_IPQ_RUMI) || defined(CONFIG_IPQ6018)
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#define QPIC_EBI2ND_BASE (0x079b0000)
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#else
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#error "QPIC NAND not supported"
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@ -86,7 +86,7 @@ ENTRY(_main)
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bl board_init_f_mem
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mov sp, r0
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#if defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ40xx)
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#if defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ6018)
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ldr r0, =__bss_start /* this is auto-relocated! */
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#ifdef CONFIG_USE_ARCH_MEMSET
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@ -156,7 +156,7 @@ here:
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cmp r0, #0
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movne sp, r0
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# endif
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#if !defined(CONFIG_ARCH_IPQ807x) && !defined(CONFIG_ARCH_IPQ40xx)
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#if !defined(CONFIG_ARCH_IPQ807x) && !defined(CONFIG_ARCH_IPQ40xx) && !defined(CONFIG_ARCH_IPQ6018)
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ldr r0, =__bss_start /* this is auto-relocated! */
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#ifdef CONFIG_USE_ARCH_MEMSET
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15
board/ipq6018/Kconfig
Normal file
15
board/ipq6018/Kconfig
Normal file
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@ -0,0 +1,15 @@
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if ARCH_IPQ6018
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config SYS_CPU
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default "ipq6018"
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config SYS_BOARD
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default "ipq6018"
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config SYS_VENDOR
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default "qca/arm"
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config SYS_CONFIG_NAME
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default "ipq6018"
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endif
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4
board/qca/arm/ipq6018/Makefile
Normal file
4
board/qca/arm/ipq6018/Makefile
Normal file
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@ -0,0 +1,4 @@
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ccflags-y += -I$(srctree)/board/qca/arm/ipq6018
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cppflags-y += -I$(srctree)/board/qca/arm/ipq6018
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obj-y := ipq6018.o
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162
board/qca/arm/ipq6018/ipq6018.c
Normal file
162
board/qca/arm/ipq6018/ipq6018.c
Normal file
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@ -0,0 +1,162 @@
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/*
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <environment.h>
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#include <asm/arch-qca-common/qpic_nand.h>
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#include <asm/arch-qca-common/gpio.h>
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#include <asm/arch-qca-common/uart.h>
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#include <ipq6018.h>
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DECLARE_GLOBAL_DATA_PTR;
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void uart2_configure_mux(void)
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{
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unsigned long cfg_rcgr;
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cfg_rcgr = readl(GCC_BLSP1_UART2_APPS_CFG_RCGR);
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/* Clear mode, src sel, src div */
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cfg_rcgr &= ~(GCC_UART_CFG_RCGR_MODE_MASK |
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GCC_UART_CFG_RCGR_SRCSEL_MASK |
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GCC_UART_CFG_RCGR_SRCDIV_MASK);
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cfg_rcgr |= ((UART2_RCGR_SRC_SEL << GCC_UART_CFG_RCGR_SRCSEL_SHIFT)
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& GCC_UART_CFG_RCGR_SRCSEL_MASK);
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cfg_rcgr |= ((UART2_RCGR_SRC_DIV << GCC_UART_CFG_RCGR_SRCDIV_SHIFT)
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& GCC_UART_CFG_RCGR_SRCDIV_MASK);
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cfg_rcgr |= ((UART2_RCGR_MODE << GCC_UART_CFG_RCGR_MODE_SHIFT)
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& GCC_UART_CFG_RCGR_MODE_MASK);
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writel(cfg_rcgr, GCC_BLSP1_UART2_APPS_CFG_RCGR);
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}
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void uart2_set_rate_mnd(unsigned int m,
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unsigned int n, unsigned int two_d)
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{
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writel(m, GCC_BLSP1_UART2_APPS_M);
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writel(NOT_N_MINUS_M(n, m), GCC_BLSP1_UART2_APPS_N);
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writel(NOT_2D(two_d), GCC_BLSP1_UART2_APPS_D);
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}
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int uart2_trigger_update(void)
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{
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unsigned long cmd_rcgr;
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int timeout = 0;
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cmd_rcgr = readl(GCC_BLSP1_UART2_APPS_CMD_RCGR);
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cmd_rcgr |= UART2_CMD_RCGR_UPDATE;
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writel(cmd_rcgr, GCC_BLSP1_UART2_APPS_CMD_RCGR);
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while (readl(GCC_BLSP1_UART2_APPS_CMD_RCGR) & UART2_CMD_RCGR_UPDATE) {
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if (timeout++ >= CLOCK_UPDATE_TIMEOUT_US) {
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printf("Timeout waiting for UART2 clock update\n");
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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cmd_rcgr = readl(GCC_BLSP1_UART2_APPS_CMD_RCGR);
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return 0;
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}
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void uart2_toggle_clock(void)
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{
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unsigned long cbcr_val;
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cbcr_val = readl(GCC_BLSP1_UART2_APPS_CBCR);
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cbcr_val |= UART2_CBCR_CLK_ENABLE;
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writel(cbcr_val, GCC_BLSP1_UART2_APPS_CBCR);
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}
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void uart2_clock_config(unsigned int m,
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unsigned int n, unsigned int two_d)
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{
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uart2_configure_mux();
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uart2_set_rate_mnd(m, n, two_d);
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uart2_trigger_update();
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uart2_toggle_clock();
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}
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void qca_serial_init(struct ipq_serial_platdata *plat)
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{
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int node, uart2_node;
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writel(1, GCC_BLSP1_UART1_APPS_CBCR);
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node = fdt_path_offset(gd->fdt_blob, "/serial@78B3000/serial_gpio");
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if (node < 0) {
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printf("Could not find serial_gpio node\n");
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return;
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}
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if (plat->port_id == 1) {
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uart2_node = fdt_path_offset(gd->fdt_blob, "uart2");
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if (uart2_node < 0) {
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printf("Could not find uart2 node\n");
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return;
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}
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node = fdt_subnode_offset(gd->fdt_blob,
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uart2_node, "serial_gpio");
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uart2_clock_config(plat->m_value, plat->n_value, plat->d_value);
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writel(1, GCC_BLSP1_UART2_APPS_CBCR);
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}
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qca_gpio_init(node);
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}
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void reset_crashdump(void)
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{
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unsigned int ret = 0;
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qca_scm_sdi();
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ret = qca_scm_dload(CLEAR_MAGIC);
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if (ret)
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printf ("Error in reseting the Magic cookie\n");
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return;
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}
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void board_nand_init(void)
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{
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return 0;
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}
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void enable_caches(void)
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{
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icache_enable();
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}
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void disable_caches(void)
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{
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icache_disable();
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}
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/**
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* Set the uuid in bootargs variable for mounting rootfilesystem
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*/
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int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_flag)
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{
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return 0;
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}
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unsigned long timer_read_counter(void)
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{
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return 0;
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}
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void reset_cpu(unsigned long a)
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{
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while(1);
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}
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109
board/qca/arm/ipq6018/ipq6018.h
Normal file
109
board/qca/arm/ipq6018/ipq6018.h
Normal file
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@ -0,0 +1,109 @@
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/*
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
|
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* only version 2 as published by the Free Software Foundation.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _IPQ6018_CDP_H_
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#define _IPQ6018_CDP_H_
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#include <configs/ipq6018.h>
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#include <asm/u-boot.h>
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#include <asm/arch-qca-common/qca_common.h>
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#define GCC_BLSP1_UART1_APPS_CBCR 0x0180203c
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#define GCC_SDCC1_BCR 0x01842000
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#define GCC_BLSP1_UART2_APPS_CFG_RCGR 0x01803038
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#define GCC_BLSP1_UART2_APPS_M 0x0180303C
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#define GCC_BLSP1_UART2_APPS_N 0x01803040
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#define GCC_BLSP1_UART2_APPS_D 0x01803044
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#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x01803034
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#define GCC_BLSP1_UART2_APPS_CBCR 0x0180302C
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#define GCC_UART_CFG_RCGR_MODE_MASK 0x3000
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#define GCC_UART_CFG_RCGR_SRCSEL_MASK 0x0700
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#define GCC_UART_CFG_RCGR_SRCDIV_MASK 0x001F
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#define GCC_UART_CFG_RCGR_MODE_SHIFT 12
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#define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8
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#define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0
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#define UART2_RCGR_SRC_SEL 0x1
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#define UART2_RCGR_SRC_DIV 0x0
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#define UART2_RCGR_MODE 0x2
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#define UART2_CMD_RCGR_UPDATE 0x1
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#define UART2_CBCR_CLK_ENABLE 0x1
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#define NOT_2D(two_d) (~two_d)
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#define NOT_N_MINUS_M(n,m) (~(n - m))
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#define CLOCK_UPDATE_TIMEOUT_US 1000
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#define CLOCK_UPDATE_TIMEOUT_US 1000
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#define KERNEL_AUTH_CMD 0x13
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struct smem_ram_ptn {
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char name[16];
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unsigned long long start;
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unsigned long long size;
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/* RAM Partition attribute: READ_ONLY, READWRITE etc. */
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unsigned attr;
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/* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
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unsigned category;
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/* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
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unsigned domain;
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/* RAM Partition type: system, bootloader, appsboot, apps etc. */
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unsigned type;
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/* reserved for future expansion without changing version number */
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unsigned reserved2, reserved3, reserved4, reserved5;
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} __attribute__ ((__packed__));
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__weak void aquantia_phy_reset_init_done(void) {}
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__weak void aquantia_phy_reset_init(void) {}
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struct smem_ram_ptable {
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#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
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#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
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unsigned magic[2];
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unsigned version;
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unsigned reserved1;
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unsigned len;
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unsigned buf;
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struct smem_ram_ptn parts[32];
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} __attribute__ ((__packed__));
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int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
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typedef enum {
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SMEM_SPINLOCK_ARRAY = 7,
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SMEM_AARM_PARTITION_TABLE = 9,
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SMEM_HW_SW_BUILD_ID = 137,
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SMEM_USABLE_RAM_PARTITION_TABLE = 402,
|
||||
SMEM_POWER_ON_STATUS_INFO = 403,
|
||||
SMEM_MACHID_INFO_LOCATION = 425,
|
||||
SMEM_IMAGE_VERSION_TABLE = 469,
|
||||
SMEM_BOOT_FLASH_TYPE = 498,
|
||||
SMEM_BOOT_FLASH_INDEX = 499,
|
||||
SMEM_BOOT_FLASH_CHIP_SELECT = 500,
|
||||
SMEM_BOOT_FLASH_BLOCK_SIZE = 501,
|
||||
SMEM_BOOT_FLASH_DENSITY = 502,
|
||||
SMEM_BOOT_DUALPARTINFO = 503,
|
||||
SMEM_PARTITION_TABLE_OFFSET = 504,
|
||||
SMEM_SPI_FLASH_ADDR_LEN = 505,
|
||||
SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
|
||||
SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN,
|
||||
SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1,
|
||||
} smem_mem_type_t;
|
||||
|
||||
#endif /* _IPQ6018_CDP_H_ */
|
||||
300
configs/ipq6018_defconfig
Normal file
300
configs/ipq6018_defconfig
Normal file
|
|
@ -0,0 +1,300 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_HAS_VBAR=y
|
||||
CONFIG_CPU_V7=y
|
||||
CONFIG_ARCH_IPQ6018=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x400
|
||||
CONFIG_SYS_MALLOC_F=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE=""
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
# CONFIG_FIT_SIGNATURE is not set
|
||||
CONFIG_SYS_EXTRA_OPTIONS=""
|
||||
CONFIG_SYS_PROMPT="IPQ6018# "
|
||||
|
||||
#
|
||||
# Commands
|
||||
#
|
||||
|
||||
#
|
||||
# Info commands
|
||||
#
|
||||
CONFIG_CMD_BDI=y
|
||||
CONFIG_CMD_CONSOLE=y
|
||||
|
||||
#
|
||||
# Boot commands
|
||||
#
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
CONFIG_CMD_BOOTM=y
|
||||
CONFIG_CMD_GO=y
|
||||
# CONFIG_CMD_RUN is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
|
||||
#
|
||||
# Environment commands
|
||||
#
|
||||
CONFIG_CMD_EXPORTENV=y
|
||||
CONFIG_CMD_IMPORTENV=y
|
||||
CONFIG_CMD_EDITENV=y
|
||||
CONFIG_CMD_SAVEENV=y
|
||||
CONFIG_CMD_ENV_EXISTS=y
|
||||
|
||||
#
|
||||
# Memory commands
|
||||
#
|
||||
CONFIG_CMD_MEMORY=y
|
||||
CONFIG_CMD_CRC32=y
|
||||
# CONFIG_LOOPW is not set
|
||||
# CONFIG_CMD_MEMTEST is not set
|
||||
# CONFIG_CMD_MX_CYCLIC is not set
|
||||
# CONFIG_CMD_MEMINFO is not set
|
||||
|
||||
#
|
||||
# Device access commands
|
||||
#
|
||||
CONFIG_CMD_DM=y
|
||||
# CONFIG_CMD_DEMO is not set
|
||||
CONFIG_CMD_LOADB=y
|
||||
CONFIG_CMD_LOADS=y
|
||||
CONFIG_CMD_FLASH=y
|
||||
# CONFIG_CMD_NAND is not set
|
||||
# CONFIG_CMD_SF is not set
|
||||
# CONFIG_CMD_SPI is not set
|
||||
# CONFIG_CMD_I2C is not set
|
||||
# CONFIG_CMD_USB is not set
|
||||
CONFIG_CMD_FPGA=y
|
||||
|
||||
#
|
||||
# Shell scripting commands
|
||||
#
|
||||
CONFIG_CMD_ECHO=y
|
||||
CONFIG_CMD_ITEST=y
|
||||
CONFIG_CMD_SOURCE=y
|
||||
CONFIG_CMD_SETEXPR=y
|
||||
|
||||
#
|
||||
# Network commands
|
||||
#
|
||||
CONFIG_CMD_NET=y
|
||||
# CONFIG_CMD_TFTPPUT is not set
|
||||
# CONFIG_CMD_TFTPSRV is not set
|
||||
# CONFIG_CMD_RARP is not set
|
||||
# CONFIG_CMD_DHCP is not set
|
||||
CONFIG_CMD_NFS=y
|
||||
# CONFIG_CMD_PING is not set
|
||||
# CONFIG_CMD_CDP is not set
|
||||
# CONFIG_CMD_SNTP is not set
|
||||
# CONFIG_CMD_DNS is not set
|
||||
# CONFIG_CMD_LINK_LOCAL is not set
|
||||
|
||||
#
|
||||
# Misc commands
|
||||
#
|
||||
# CONFIG_CMD_TIME is not set
|
||||
CONFIG_CMD_MISC=y
|
||||
# CONFIG_CMD_TIMER is not set
|
||||
|
||||
#
|
||||
# Boot timing
|
||||
#
|
||||
# CONFIG_BOOTSTAGE is not set
|
||||
CONFIG_BOOTSTAGE_USER_COUNT=20
|
||||
CONFIG_BOOTSTAGE_STASH_ADDR=0
|
||||
CONFIG_BOOTSTAGE_STASH_SIZE=4096
|
||||
|
||||
#
|
||||
# Power commands
|
||||
#
|
||||
|
||||
#
|
||||
# Security commands
|
||||
#
|
||||
CONFIG_SUPPORT_OF_CONTROL=y
|
||||
|
||||
#
|
||||
# Device Tree Control
|
||||
#
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_SEPARATE=y
|
||||
# CONFIG_OF_EMBED is not set
|
||||
CONFIG_NET=y
|
||||
# CONFIG_NET_RANDOM_ETHADDR is not set
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_DM=y
|
||||
CONFIG_DM_WARN=y
|
||||
CONFIG_DM_DEVICE_REMOVE=y
|
||||
CONFIG_DM_STDIO=y
|
||||
CONFIG_DM_SEQ_ALIAS=y
|
||||
# CONFIG_REGMAP is not set
|
||||
# CONFIG_DEVRES is not set
|
||||
CONFIG_SIMPLE_BUS=y
|
||||
# CONFIG_CLK is not set
|
||||
# CONFIG_CPU is not set
|
||||
|
||||
#
|
||||
# Hardware crypto devices
|
||||
#
|
||||
# CONFIG_FSL_CAAM is not set
|
||||
|
||||
#
|
||||
# Demo for driver model
|
||||
#
|
||||
# CONFIG_DM_DEMO is not set
|
||||
|
||||
#
|
||||
# DFU support
|
||||
#
|
||||
# CONFIG_DFU_TFTP is not set
|
||||
|
||||
#
|
||||
# GPIO Support
|
||||
#
|
||||
# CONFIG_LPC32XX_GPIO is not set
|
||||
# CONFIG_VYBRID_GPIO is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
# CONFIG_DM_I2C_COMPAT is not set
|
||||
# CONFIG_CROS_EC_KEYB is not set
|
||||
|
||||
#
|
||||
# LED Support
|
||||
#
|
||||
# CONFIG_LED is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_CROS_EC is not set
|
||||
# CONFIG_FSL_SEC_MON is not set
|
||||
# CONFIG_PCA9551_LED is not set
|
||||
# CONFIG_RESET is not set
|
||||
|
||||
#
|
||||
# MMC Host controller Support
|
||||
#
|
||||
# CONFIG_DM_MMC is not set
|
||||
|
||||
#
|
||||
# NAND Device Support
|
||||
#
|
||||
# CONFIG_NAND_DENALI is not set
|
||||
# CONFIG_NAND_VF610_NFC is not set
|
||||
# CONFIG_NAND_PXA3XX is not set
|
||||
|
||||
#
|
||||
# Generic NAND options
|
||||
#
|
||||
|
||||
#
|
||||
# SPI Flash Support
|
||||
#
|
||||
# CONFIG_SPI_FLASH is not set
|
||||
# CONFIG_DM_ETH is not set
|
||||
# CONFIG_PHYLIB is not set
|
||||
# CONFIG_NETDEVICES is not set
|
||||
|
||||
#
|
||||
# PCI
|
||||
#
|
||||
# CONFIG_DM_PCI is not set
|
||||
|
||||
#
|
||||
# Pin controllers
|
||||
#
|
||||
# CONFIG_PINCTRL is not set
|
||||
|
||||
#
|
||||
# Power
|
||||
#
|
||||
# CONFIG_DM_PMIC is not set
|
||||
# CONFIG_DM_REGULATOR is not set
|
||||
# CONFIG_RAM is not set
|
||||
|
||||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
# CONFIG_DM_RTC is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
CONFIG_REQUIRE_SERIAL_CONSOLE=y
|
||||
# CONFIG_DEBUG_UART is not set
|
||||
|
||||
#
|
||||
# Sound support
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# SPI Support
|
||||
#
|
||||
# CONFIG_FSL_ESPI is not set
|
||||
# CONFIG_TI_QSPI is not set
|
||||
# CONFIG_DM_THERMAL is not set
|
||||
|
||||
#
|
||||
# TPM support
|
||||
#
|
||||
# CONFIG_USB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_VIDEO_VESA is not set
|
||||
# CONFIG_VIDEO_LCD_ANX9804 is not set
|
||||
# CONFIG_VIDEO_LCD_SSD2828 is not set
|
||||
# CONFIG_DISPLAY_PORT is not set
|
||||
# CONFIG_VIDEO_TEGRA124 is not set
|
||||
# CONFIG_VIDEO_BRIDGE is not set
|
||||
# CONFIG_PHYS_TO_BUS is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
|
||||
CONFIG_HAVE_PRIVATE_LIBGCC=y
|
||||
# CONFIG_USE_PRIVATE_LIBGCC is not set
|
||||
CONFIG_SYS_HZ=1000
|
||||
# CONFIG_SYS_VSNPRINTF is not set
|
||||
CONFIG_REGEX=y
|
||||
# CONFIG_LIB_RAND is not set
|
||||
# CONFIG_CMD_DHRYSTONE is not set
|
||||
# CONFIG_RSA is not set
|
||||
# CONFIG_TPM is not set
|
||||
|
||||
#
|
||||
# Hashing Support
|
||||
#
|
||||
# CONFIG_SHA1 is not set
|
||||
# CONFIG_SHA256 is not set
|
||||
# CONFIG_SHA_HW_ACCEL is not set
|
||||
|
||||
#
|
||||
# Compression Support
|
||||
#
|
||||
# CONFIG_LZ4 is not set
|
||||
# CONFIG_ERRNO_STR is not set
|
||||
# CONFIG_UNIT_TEST is not set
|
||||
|
|
@ -8,6 +8,7 @@
|
|||
obj-$(CONFIG_ARCH_IPQ807x) += ipq_gpio.o
|
||||
obj-$(CONFIG_ARCH_IPQ806x) += ipq_gpio.o
|
||||
obj-$(CONFIG_ARCH_IPQ40xx) += ipq_gpio.o
|
||||
obj-$(CONFIG_ARCH_IPQ6018) += ipq_gpio.o
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o
|
||||
obj-$(CONFIG_AXP_GPIO) += axp_gpio.o
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ cppflags-y += -I$(srctree)/board/qca/ipq40xx
|
|||
obj-$(CONFIG_ARCH_IPQ807x) += qca_uart.o
|
||||
obj-$(CONFIG_ARCH_IPQ806x) += qca_uart.o
|
||||
obj-$(CONFIG_ARCH_IPQ40xx) += qca_uart.o
|
||||
obj-$(CONFIG_ARCH_IPQ6018) += qca_uart.o
|
||||
ifdef CONFIG_DM_SERIAL
|
||||
obj-y += serial-uclass.o
|
||||
obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
|
||||
|
|
|
|||
|
|
@ -35,6 +35,9 @@ typedef volatile unsigned char vu_char;
|
|||
#elif defined(CONFIG_IPQ806X)
|
||||
#include <../board/qca/arm/ipq806x/ipq806x.h>
|
||||
|
||||
#elif defined(CONFIG_IPQ6018)
|
||||
#include <../board/qca/arm/ipq6018/ipq6018.h>
|
||||
|
||||
#elif defined(CONFIG_IPQ_RUMI)
|
||||
#include <../board/qca/arm/ipq807x/ipq807x.h>
|
||||
#endif
|
||||
|
|
@ -403,7 +406,7 @@ ulong getenv_hex(const char *varname, ulong default_val);
|
|||
* Return -1 if variable does not exist (default to true)
|
||||
*/
|
||||
int getenv_yesno(const char *var);
|
||||
#if defined(CONFIG_IPQ40XX_ENV) || defined(CONFIG_IPQ807X_ENV) || defined(CONFIG_IPQ806X_ENV)
|
||||
#if defined(CONFIG_IPQ40XX_ENV) || defined(CONFIG_IPQ807X_ENV) || defined(CONFIG_IPQ806X_ENV) || defined(CONFIG_IPQ6018_ENV)
|
||||
extern int (*saveenv)(void);
|
||||
#else
|
||||
int saveenv (void);
|
||||
|
|
|
|||
195
include/configs/ipq6018.h
Normal file
195
include/configs/ipq6018.h
Normal file
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _IPQ6018_H
|
||||
#define _IPQ6018_H
|
||||
|
||||
#ifndef DO_DEPS_ONLY
|
||||
#include <generated/asm-offsets.h>
|
||||
#endif
|
||||
|
||||
#define CONFIG_IPQ6018
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
#define CONFIG_IPQ6018_UART
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN 0x1000000
|
||||
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (256 << 10))
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE 1
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
115200}
|
||||
|
||||
#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */
|
||||
|
||||
/*
|
||||
|
||||
svc_sp --> --------------
|
||||
irq_sp --> | |
|
||||
fiq_sp --> | |
|
||||
bd --> | |
|
||||
gd --> | |
|
||||
pgt --> | |
|
||||
malloc --> | |
|
||||
text_base --> |------------|
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\
|
||||
CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\
|
||||
GENERATED_BD_INFO_SIZE)
|
||||
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#define TLMM_BASE 0x01000000
|
||||
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000)
|
||||
#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x4A900000
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
|
||||
#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20))
|
||||
|
||||
#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE
|
||||
#define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE
|
||||
#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100)
|
||||
|
||||
#define CONFIG_OF_COMBINE 1
|
||||
|
||||
#define CONFIG_QCA_SMEM_BASE 0x4AB00000
|
||||
|
||||
#define CONFIG_IPQ_FDT_HIGH 0x4A400000
|
||||
#define CONFIG_IPQ_NO_MACS 6
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
/*
|
||||
* IPQ_TFTP_MIN_ADDR: Starting address of Linux HLOS region.
|
||||
* CONFIG_TZ_END_ADDR: Ending address of Trust Zone and starting
|
||||
* address of WLAN Area.
|
||||
* TFTP file can only be written in Linux HLOS region and WLAN AREA.
|
||||
*/
|
||||
#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20))
|
||||
#define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21))
|
||||
#define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <compiler.h>
|
||||
extern loff_t board_env_offset;
|
||||
extern loff_t board_env_range;
|
||||
extern loff_t board_env_size;
|
||||
#endif
|
||||
|
||||
#define CONFIG_IPQ6018_ENV 1
|
||||
#define CONFIG_ENV_OFFSET board_env_offset
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX
|
||||
#define CONFIG_ENV_RANGE board_env_range
|
||||
#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (1024 << 10))
|
||||
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
|
||||
/*
|
||||
* NAND Flash Configs
|
||||
*/
|
||||
|
||||
/* CONFIG_QPIC_NAND: QPIC NAND in BAM mode
|
||||
* CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode.
|
||||
* BAM is enabled by default.
|
||||
*/
|
||||
#define CONFIG_QPIC_NAND
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_YAFFS
|
||||
#define CONFIG_SYS_NAND_SELF_INIT
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/*
|
||||
* Expose SPI driver as a pseudo NAND driver to make use
|
||||
* of U-Boot's MTD framework.
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \
|
||||
CONFIG_IPQ_MAX_SPI_DEVICE
|
||||
|
||||
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
|
||||
|
||||
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
|
||||
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
|
||||
|
||||
#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX
|
||||
#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
|
||||
|
||||
#define QCA_SPI_NOR_DEVICE "spi0.0"
|
||||
#define CONFIG_QUP_SPI_USE_DMA 1
|
||||
|
||||
/*
|
||||
* U-Boot Env Configs
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
|
||||
/* NSS firmware loaded using bootm */
|
||||
#define CONFIG_BOOTCOMMAND "bootm"
|
||||
#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8"
|
||||
#define QCA_ROOT_FS_PART_NAME "rootfs"
|
||||
|
||||
#define CONFIG_BOOTDELAY 2
|
||||
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define NUM_ALT_PARTITION 16
|
||||
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_RBTREE
|
||||
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
/*
|
||||
* Below Configs need to be updated after enabling reset_crashdump
|
||||
* Included now to avoid build failure
|
||||
*/
|
||||
#define SET_MAGIC 0x1
|
||||
#define CLEAR_MAGIC 0x0
|
||||
#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9
|
||||
#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10
|
||||
#define SCM_CMD_TZ_PSHOLD 0x15
|
||||
/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
|
||||
* Cache flush and invalidation based on L1 cache, so the cache line
|
||||
* size is configured to 64 */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
/*#define CONFIG_SYS_DCACHE_OFF*/
|
||||
|
||||
/* Enabling this flag will report any L2 errors.
|
||||
* By default we are disabling it */
|
||||
/*#define CONFIG_IPQ_REPORT_L2ERR*/
|
||||
|
||||
#endif /* _IPQ6018_H */
|
||||
59
include/dt-bindings/qcom/gpio-ipq6018.h
Normal file
59
include/dt-bindings/qcom/gpio-ipq6018.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_IPQ6018_GPIO_H__
|
||||
#define __DT_BINDINGS_IPQ6018_GPIO_H__
|
||||
|
||||
/* GPIO TLMM: Direction */
|
||||
#define GPIO_INPUT 0
|
||||
#define GPIO_OUTPUT 1
|
||||
|
||||
/* GPIO TLMM: Output value */
|
||||
#define GPIO_OUT_LOW 0
|
||||
#define GPIO_OUT_HIGH 1
|
||||
|
||||
/* GPIO TLMM: Pullup/Pulldown */
|
||||
#define GPIO_NO_PULL 0
|
||||
#define GPIO_PULL_DOWN 1
|
||||
#define GPIO_KEEPER 2
|
||||
#define GPIO_PULL_UP 3
|
||||
|
||||
/* GPIO TLMM: Drive Strength */
|
||||
#define GPIO_2MA 0
|
||||
#define GPIO_4MA 1
|
||||
#define GPIO_6MA 2
|
||||
#define GPIO_8MA 3
|
||||
#define GPIO_10MA 4
|
||||
#define GPIO_12MA 5
|
||||
#define GPIO_14MA 6
|
||||
#define GPIO_16MA 7
|
||||
|
||||
/* GPIO TLMM: Status */
|
||||
#define GPIO_OE_DISABLE 0
|
||||
#define GPIO_OE_ENABLE 1
|
||||
|
||||
/* GPIO VM */
|
||||
#define GPIO_VM_ENABLE 1
|
||||
#define GPIO_VM_DISABLE 0
|
||||
|
||||
/* GPIO OD */
|
||||
#define GPIO_OD_ENABLE 1
|
||||
#define GPIO_OD_DISABLE 0
|
||||
|
||||
/* GPIO PULLUP RES */
|
||||
#define GPIO_PULL_RES0 0
|
||||
#define GPIO_PULL_RES1 1
|
||||
#define GPIO_PULL_RES2 2
|
||||
#define GPIO_PULL_RES3 3
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue