diff --git a/arch/arm/dts/ipq9574-al01-c1.dts b/arch/arm/dts/ipq9574-al01-c1.dts index a7a8ac50bf..69b4fb1c48 100644 --- a/arch/arm/dts/ipq9574-al01-c1.dts +++ b/arch/arm/dts/ipq9574-al01-c1.dts @@ -158,7 +158,7 @@ }; ess-switch { - switch_mac_mode = ; + switch_mac_mode0 = ; switch_mac_mode1 = ; /* Unused */ switch_mac_mode2 = ; qca807x_gpio = <60>; diff --git a/arch/arm/dts/ipq9574-al02-c1.dts b/arch/arm/dts/ipq9574-al02-c1.dts index 7fb07f711c..7c844f3180 100644 --- a/arch/arm/dts/ipq9574-al02-c1.dts +++ b/arch/arm/dts/ipq9574-al02-c1.dts @@ -157,7 +157,7 @@ }; ess-switch { - switch_mac_mode = ; + switch_mac_mode0 = ; switch_mac_mode1 = ; switch_mac_mode2 = ; aquantia_gpio = <37>; diff --git a/arch/arm/dts/ipq9574-db-al01-c1.dts b/arch/arm/dts/ipq9574-db-al01-c1.dts index 646853df17..ffa1abec7c 100644 --- a/arch/arm/dts/ipq9574-db-al01-c1.dts +++ b/arch/arm/dts/ipq9574-db-al01-c1.dts @@ -158,7 +158,7 @@ }; ess-switch { - switch_mac_mode = ; + switch_mac_mode0 = ; switch_mac_mode1 = ; switch_mac_mode2 = ; qca807x_gpio = <60>; diff --git a/arch/arm/dts/ipq9574-emulation.dts b/arch/arm/dts/ipq9574-emulation.dts index 71c4a9ad87..8622b443c4 100644 --- a/arch/arm/dts/ipq9574-emulation.dts +++ b/arch/arm/dts/ipq9574-emulation.dts @@ -110,6 +110,5 @@ switch_mac_mode0 = ; switch_mac_mode1 = ; switch_mac_mode2 = ; - uniphy0_port5 = <1>; }; }; diff --git a/board/qca/arm/ipq9574/ipq9574.c b/board/qca/arm/ipq9574/ipq9574.c index 068fe326ca..cd33abbe1c 100644 --- a/board/qca/arm/ipq9574/ipq9574.c +++ b/board/qca/arm/ipq9574/ipq9574.c @@ -735,7 +735,6 @@ void set_function_select_as_mdc_mdio(void) void eth_clock_enable(void) { int reg_val, reg_val1, mode, i; - int gcc_pll_base = 0x0009B780; int node; /* Clock init */ @@ -773,7 +772,7 @@ void eth_clock_enable(void) /* SYSNOC frequency 343M */ reg_val = readl(0x182E004 + 4); reg_val &= ~0x7ff; - writel(reg_val | 206, 0x182E004 + 4); + writel(reg_val | 0x206, 0x182E004 + 4); /* Update Config */ reg_val = readl(0x182E004); writel(reg_val | 0x1, 0x182E004); @@ -853,21 +852,6 @@ void eth_clock_enable(void) writel(0x1, NSS_CC_PORT5_TX_CMD_RCGR); writel(0x2, NSS_CC_PORT5_TX_CMD_RCGR); - /* CMN BLK init */ - reg_val = readl(gcc_pll_base + 4); - /* CMN BLK Mode: INTERNAL_48MHZ */ - reg_val = (reg_val&0xfffffdf0) | 0x7; - writel(reg_val, gcc_pll_base + 0x4); - reg_val = readl(gcc_pll_base); - reg_val = reg_val | 0x40; - writel(reg_val, gcc_pll_base); - mdelay(1); - reg_val = reg_val & (~0x40); - writel(reg_val, gcc_pll_base); - mdelay(1); - writel(0xbf, gcc_pll_base); - mdelay(1); - /* Uniphy Port5 clock source set */ reg_val = readl(NSS_CC_PORT_SPEED_DIVIDER + 0x64); reg_val1 = readl(NSS_CC_PORT_SPEED_DIVIDER + 0x70); diff --git a/board/qca/arm/ipq9574/ipq9574.h b/board/qca/arm/ipq9574/ipq9574.h index 1476efa510..61adaa61c3 100644 --- a/board/qca/arm/ipq9574/ipq9574.h +++ b/board/qca/arm/ipq9574/ipq9574.h @@ -53,7 +53,6 @@ #define GCC_NSSNOC_SNOC_1_CBCR 0x181707C #define GCC_MEM_NOC_SNOC_AXI_CBCR 0x1819018 #define GCC_IMEM_AXI_CBCR 0x180E004 -#define NSS_CC_PORT1_RX_CBCR_ADDR 0x39B281A0 #define NSS_CC_UNIPHY_PORT1_RX_ADDR 0x39B28904 #define NSS_CC_PPE_RESET_ADDR 0x39B28A08 #define NSS_CC_UNIPHY_MISC_RESET 0x39B28A24 diff --git a/drivers/net/ipq9574/ipq9574_edma.c b/drivers/net/ipq9574/ipq9574_edma.c index b9517bc80d..0414a3fdcd 100644 --- a/drivers/net/ipq9574/ipq9574_edma.c +++ b/drivers/net/ipq9574/ipq9574_edma.c @@ -677,6 +677,9 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw) for (j = 0; j < rxfill_ring->count; j++) { rxfill_desc = IPQ9574_EDMA_RXFILL_DESC(rxfill_ring, j); rxfill_desc->rdes0 = virt_to_phys(rx_buf); + rxfill_desc->rdes1 = 0; + rxfill_desc->rdes2 = 0; + rxfill_desc->rdes3 = 0; rx_buf += PKTSIZE_ALIGN; pr_debug("Ring %d: rxfill ring dis0 ptr = %p, rxfill ring dis0 dma = %u\n", j, rxfill_desc, (unsigned int)rxfill_desc->rdes0); @@ -813,6 +816,13 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw) for (j = 0; j < txdesc_ring->count; j++) { tx_desc = IPQ9574_EDMA_TXDESC_DESC(txdesc_ring, j); tx_desc->tdes0 = virt_to_phys(tx_buf); + tx_desc->tdes1 = 0; + tx_desc->tdes2 = 0; + tx_desc->tdes3 = 0; + tx_desc->tdes4 = 0; + tx_desc->tdes5 = 0; + tx_desc->tdes6 = 0; + tx_desc->tdes7 = 0; tx_buf += IPQ9574_EDMA_TX_BUFF_SIZE; pr_debug("Ring %d: txdesc ring dis0 ptr = %p, txdesc ring dis0 dma = %u\n", j, tx_desc, (unsigned int)tx_desc->tdes0); @@ -1928,7 +1938,7 @@ int ipq9574_edma_init(void *edma_board_cfg) mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1); if (mode < 0) { - printf("Error:switch_mac_mode not specified in dts"); + printf("Error:switch_mac_mode0 not specified in dts"); return mode; } #endif @@ -2072,6 +2082,7 @@ int ipq9574_edma_init(void *edma_board_cfg) break; #endif default: + printf("\nphy id not matching, calling default qca807x ops"); ipq_qca8075_phy_map_ops(&ipq9574_edma_dev[i]->ops[phy_id]); break; } diff --git a/drivers/net/ipq9574/ipq9574_edma.h b/drivers/net/ipq9574/ipq9574_edma.h index 3a08d9b7e0..3accdb891c 100644 --- a/drivers/net/ipq9574/ipq9574_edma.h +++ b/drivers/net/ipq9574/ipq9574_edma.h @@ -19,7 +19,7 @@ #define __IPQ9574_EDMA__ #define IPQ9574_NSS_DP_START_PHY_PORT 1 -#define IPQ9574_NSS_DP_MAX_PHY_PORTS 7 +#define IPQ9574_NSS_DP_MAX_PHY_PORTS 6 #define IPQ9574_EDMA_BUF_SIZE 2000 #define IPQ9574_EDMA_DEVICE_NODE_NAME "edma" diff --git a/drivers/net/ipq_common/ipq_phy.h b/drivers/net/ipq_common/ipq_phy.h index bb39d171bd..41a7c70b1b 100755 --- a/drivers/net/ipq_common/ipq_phy.h +++ b/drivers/net/ipq_common/ipq_phy.h @@ -18,7 +18,7 @@ #include #define PHY_MAX 6 -#define IPQ9574_PHY_MAX 7 +#define IPQ9574_PHY_MAX 6 #define IPQ6018_PHY_MAX 5 #define MDIO_CTRL_0_REG 0x00090040 #define MDIO_CTRL_0_DIV(x) (x << 0)