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drivers: net: ipq: Update mdio macros

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This patch renames the GCC macro which was added
for QCA8084 PHY to fix the conflict with similar
macro defined in ipq5018 platform.

Additionally, this patch also moves all QCA8084
macro definitions in MDIO driver under QCA8084_PHY
config.

Change-Id: Icd62bf260ffeae64bf67c0c1a58afb6ac4999e22
Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
This commit is contained in:
Selvam Sathappan Periakaruppan 2022-05-25 19:03:17 +05:30
parent beba2c6bb3
commit 207cf5ff59
2 changed files with 5 additions and 3 deletions
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4
drivers/net/ipq_common/ipq_mdio.c
View file

@ -298,9 +298,9 @@ void ipq_clock_init(void)
ipq_clk_reset(EPHY3_SYS_CBCR);
/* Deassert EPHY DSP */
val = ipq_mii_read(GCC_GEPHY_MISC);
val = ipq_mii_read(QCA8084_GCC_GEPHY_MISC);
val &= ~GENMASK(4, 0);
ipq_mii_write(GCC_GEPHY_MISC, val);
ipq_mii_write(QCA8084_GCC_GEPHY_MISC, val);
/* Enable efuse loading into analog circuit */
val = ipq_mii_read(EPHY_CFG);

4
drivers/net/ipq_common/ipq_mdio.h
View file

@ -35,6 +35,7 @@
#define IPQ_MDIO_RETRY 1000
#define IPQ_MDIO_DELAY 5
#ifdef CONFIG_QCA8084_PHY
/* QCA8084 related MDIO Init macros */
#define UNIPHY_CFG 0xC90F014
#define EPHY_CFG 0xC90F018
@ -45,7 +46,7 @@
#define EPHY1_SYS_CBCR 0xC8001B4
#define EPHY2_SYS_CBCR 0xC8001B8
#define EPHY3_SYS_CBCR 0xC8001BC
#define GCC_GEPHY_MISC 0xC800304
#define QCA8084_GCC_GEPHY_MISC 0xC800304
#define PHY_ADDR_LENGTH 5
#define PHY_ADDR_NUM 4
#define UNIPHY_ADDR_NUM 3
@ -53,5 +54,6 @@
#define MII_LOW_ADDR_PREFIX 0x10
DEFINE_MUTEX(switch_mdio_lock);
#endif /* End QCA8084_PHY */
#endif /* End _IPQ_MDIO_H */