diff --git a/drivers/net/ipq_common/ipq_mdio.c b/drivers/net/ipq_common/ipq_mdio.c
index 8ed8c3fb00..0219f5e937 100644
--- a/drivers/net/ipq_common/ipq_mdio.c
+++ b/drivers/net/ipq_common/ipq_mdio.c
@@ -298,9 +298,9 @@ void ipq_clock_init(void)
 	ipq_clk_reset(EPHY3_SYS_CBCR);
 
 	/* Deassert EPHY DSP */
-	val = ipq_mii_read(GCC_GEPHY_MISC);
+	val = ipq_mii_read(QCA8084_GCC_GEPHY_MISC);
 	val &= ~GENMASK(4, 0);
-	ipq_mii_write(GCC_GEPHY_MISC, val);
+	ipq_mii_write(QCA8084_GCC_GEPHY_MISC, val);
 
 	/* Enable efuse loading into analog circuit */
 	val = ipq_mii_read(EPHY_CFG);
diff --git a/drivers/net/ipq_common/ipq_mdio.h b/drivers/net/ipq_common/ipq_mdio.h
index fdd79d3914..a83a6e4a9b 100644
--- a/drivers/net/ipq_common/ipq_mdio.h
+++ b/drivers/net/ipq_common/ipq_mdio.h
@@ -35,6 +35,7 @@
 #define IPQ_MDIO_RETRY				1000
 #define IPQ_MDIO_DELAY				5
 
+#ifdef CONFIG_QCA8084_PHY
 /* QCA8084 related MDIO Init macros */
 #define UNIPHY_CFG				0xC90F014
 #define EPHY_CFG				0xC90F018
@@ -45,7 +46,7 @@
 #define EPHY1_SYS_CBCR				0xC8001B4
 #define EPHY2_SYS_CBCR				0xC8001B8
 #define EPHY3_SYS_CBCR				0xC8001BC
-#define GCC_GEPHY_MISC				0xC800304
+#define QCA8084_GCC_GEPHY_MISC			0xC800304
 #define PHY_ADDR_LENGTH				5
 #define PHY_ADDR_NUM				4
 #define UNIPHY_ADDR_NUM				3
@@ -53,5 +54,6 @@
 #define MII_LOW_ADDR_PREFIX			0x10
 
 DEFINE_MUTEX(switch_mdio_lock);
+#endif /* End QCA8084_PHY */
 
 #endif /* End _IPQ_MDIO_H */