From 14fe9facffa3010bd45cc8ac7046f12464cf532d Mon Sep 17 00:00:00 2001 From: Rajkumar Ayyasamy Date: Mon, 19 Mar 2018 11:47:02 +0530 Subject: [PATCH] ipq806x: set 48MHz clk for mmc data transfer mode As 52Mhz clk does not have 50% dutycycle, setting 48MHz clk for mmc data transfer mode Change-Id: Id9c0ce07fe652df7d575c5ea11f1d83eab0fb24c Signed-off-by: Rajkumar Ayyasamy --- drivers/clk/ipq806x_clk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/ipq806x_clk.c b/drivers/clk/ipq806x_clk.c index f801bd2d90..e95fe9137f 100644 --- a/drivers/clk/ipq806x_clk.c +++ b/drivers/clk/ipq806x_clk.c @@ -600,10 +600,10 @@ void emmc_clock_config(int mode) udelay(10); } if (mode == MMC_DATA_TRANSFER_MODE) { - /*52 MHz pll8 */ - emmc_set_rate_mnd(13, 32); + /*48 MHz pll8 */ + emmc_set_rate_mnd(1, 8); emmc_pll_vote_clk_enable(); - emmc_local_clock_enable(13, 32, 3, 3, 3); + emmc_local_clock_enable(1, 8, 1, 3, 3); emmc_clock_reset(); udelay(10); }