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ipq9574: Enable NSS_NOC clocks required for ethernet

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In order to access DDR from NSS Block, we require the
MEM NOC to be enabled. Without enabling this, NSS Block
will not be able to access the DDR.

Similarly, we also enable other NSS NOC clocks which
are required for accessing various blocks.

Change-Id: I3c470bd182516f3415ff3b7e523e9474e3e6ed41
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This commit is contained in:
Selvam Sathappan Periakaruppan 2021-07-27 20:29:56 +05:30
parent 85e6f1ca5a
commit 027fa4db92
2 changed files with 22 additions and 0 deletions
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15
board/qca/arm/ipq9574/ipq9574.c
View file

@ -738,6 +738,21 @@ void eth_clock_enable(void)
int node;
/* Clock init */
/* Enable required NSSNOC clocks */
writel(readl(GCC_MEM_NOC_NSSNOC_CLK) | GCC_CBCR_CLK_ENABLE,
GCC_MEM_NOC_NSSNOC_CLK);
writel(readl(GCC_NSSCFG_CLK) | GCC_CBCR_CLK_ENABLE, GCC_NSSCFG_CLK);
writel(readl(GCC_NSSNOC_ATB_CLK) | GCC_CBCR_CLK_ENABLE,
GCC_NSSNOC_ATB_CLK);
writel(readl(GCC_NSSNOC_MEM_NOC_1_CLK) | GCC_CBCR_CLK_ENABLE,
GCC_NSSNOC_MEM_NOC_1_CLK);
writel(readl(GCC_NSSNOC_MEMNOC_CLK) | GCC_CBCR_CLK_ENABLE,
GCC_NSSNOC_MEMNOC_CLK);
writel(readl(GCC_NSSNOC_QOSGEN_REF_CLK) | GCC_CBCR_CLK_ENABLE,
GCC_NSSNOC_QOSGEN_REF_CLK);
writel(readl(GCC_NSSNOC_TIMEOUT_REF_CLK) | GCC_CBCR_CLK_ENABLE,
GCC_NSSNOC_TIMEOUT_REF_CLK);
/* Frequency init */
/* GCC NSS frequency 100M */
reg_val = readl(0x39B28104 + 4);

7
board/qca/arm/ipq9574/ipq9574.h
View file

@ -49,6 +49,13 @@
#define NSS_CC_NSSNOC_PPE_CFG_CBCR 0x39B28248
#define NSS_CC_PPE_SWITCH_BTQ_ADDR 0x39B2827C
#define GCC_MDIO_AHB_CBCR_ADDR 0x1817040
#define GCC_MEM_NOC_NSSNOC_CLK 0x01819014
#define GCC_NSSCFG_CLK 0x0181702C
#define GCC_NSSNOC_ATB_CLK 0x01817014
#define GCC_NSSNOC_MEM_NOC_1_CLK 0x01817084
#define GCC_NSSNOC_MEMNOC_CLK 0x01817024
#define GCC_NSSNOC_QOSGEN_REF_CLK 0x0181701C
#define GCC_NSSNOC_TIMEOUT_REF_CLK 0x01817020
#define GCC_NSSNOC_SNOC_CBCR 0x1817028
#define GCC_NSSNOC_SNOC_1_CBCR 0x181707C
#define GCC_MEM_NOC_SNOC_AXI_CBCR 0x1819018