diff --git a/board/qca/arm/ipq9574/ipq9574.c b/board/qca/arm/ipq9574/ipq9574.c
index cd33abbe1c..394c88e757 100644
--- a/board/qca/arm/ipq9574/ipq9574.c
+++ b/board/qca/arm/ipq9574/ipq9574.c
@@ -738,6 +738,21 @@ void eth_clock_enable(void)
 	int node;
 
 	/* Clock init */
+	/* Enable required NSSNOC clocks */
+	writel(readl(GCC_MEM_NOC_NSSNOC_CLK) | GCC_CBCR_CLK_ENABLE,
+		GCC_MEM_NOC_NSSNOC_CLK);
+	writel(readl(GCC_NSSCFG_CLK) | GCC_CBCR_CLK_ENABLE, GCC_NSSCFG_CLK);
+	writel(readl(GCC_NSSNOC_ATB_CLK) | GCC_CBCR_CLK_ENABLE,
+		GCC_NSSNOC_ATB_CLK);
+	writel(readl(GCC_NSSNOC_MEM_NOC_1_CLK) | GCC_CBCR_CLK_ENABLE,
+		GCC_NSSNOC_MEM_NOC_1_CLK);
+	writel(readl(GCC_NSSNOC_MEMNOC_CLK) | GCC_CBCR_CLK_ENABLE,
+		GCC_NSSNOC_MEMNOC_CLK);
+	writel(readl(GCC_NSSNOC_QOSGEN_REF_CLK) | GCC_CBCR_CLK_ENABLE,
+		GCC_NSSNOC_QOSGEN_REF_CLK);
+	writel(readl(GCC_NSSNOC_TIMEOUT_REF_CLK) | GCC_CBCR_CLK_ENABLE,
+		GCC_NSSNOC_TIMEOUT_REF_CLK);
+
 	/* Frequency init */
 	/* GCC NSS frequency 100M */
 	reg_val = readl(0x39B28104 + 4);
diff --git a/board/qca/arm/ipq9574/ipq9574.h b/board/qca/arm/ipq9574/ipq9574.h
index 61adaa61c3..260f07cbe0 100644
--- a/board/qca/arm/ipq9574/ipq9574.h
+++ b/board/qca/arm/ipq9574/ipq9574.h
@@ -49,6 +49,13 @@
 #define NSS_CC_NSSNOC_PPE_CFG_CBCR		0x39B28248
 #define NSS_CC_PPE_SWITCH_BTQ_ADDR		0x39B2827C
 #define GCC_MDIO_AHB_CBCR_ADDR			0x1817040
+#define GCC_MEM_NOC_NSSNOC_CLK			0x01819014
+#define GCC_NSSCFG_CLK				0x0181702C
+#define GCC_NSSNOC_ATB_CLK			0x01817014
+#define GCC_NSSNOC_MEM_NOC_1_CLK		0x01817084
+#define GCC_NSSNOC_MEMNOC_CLK			0x01817024
+#define GCC_NSSNOC_QOSGEN_REF_CLK		0x0181701C
+#define GCC_NSSNOC_TIMEOUT_REF_CLK		0x01817020
 #define GCC_NSSNOC_SNOC_CBCR			0x1817028
 #define GCC_NSSNOC_SNOC_1_CBCR			0x181707C
 #define GCC_MEM_NOC_SNOC_AXI_CBCR		0x1819018