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4.9 KiB
4.9 KiB
RTL8214FC/RTL8218B Register Layout
This is a sum up of what we got from the comments in the GPL sources. Additionally some SerDes registers where identified that work similar like the RTL838x/RTL839x built in SerDes.
| Page | Register | Bits | Feature | Documentation |
|---|---|---|---|---|
| Page | Register | Bits | PTP feature | Absolute 0x1600 |
| 0x2C0 | 0x10 | 15:00 | PTP_TIME_NSEC_L | |
| 0x2C0 | 0x11 | 15:00 | PTP_TIME_NSEC_H | |
| 0x2C0 | 0x12 | 15:00 | PTP_TIME_SEC_L | |
| 0x2C0 | 0x13 | 15:00 | PTP_TIME_SEC_H | |
| 0x2C0 | 0x14 | 15:00 | PTP_TIME_CFG_0 | |
| 0x2C0 | 0x15 | 15:00 | PTP_OTAG_TPID | |
| 0x2C0 | 0x16 | 15:00 | PTP_ITAG_TPID | |
| 0x2C0 | 0x17 | 15:00 | PTP_MAC_ADDR_L | |
| 0x2C1 | 0x10 | 15:00 | PTP_MAC_ADDR_M | |
| 0x2C1 | 0x11 | 15:00 | PTP_MAC_ADDR_H | |
| 0x2C1 | 0x12 | 15:00 | PTP_TIME_NSEC_L_RO | |
| 0x2C1 | 0x13 | 15:00 | PTP_TIME_NSEC_H_RO | |
| 0x2C1 | 0x14 | 15:00 | PTP_TIME_SEC_L_RO | |
| 0x2C1 | 0x15 | 15:00 | PTP_TIME_SEC_H_RO | |
| 0x2C1 | 0x16 | 15:00 | PTP_TIME_CFG_1 | |
| 0x2C1 | 0x17 | 15:00 | PTP_TIME_INT_STS_P | |
| Page | Register | Bits | MAC SerDes 0 - page 0 | Absolute 0x2020 |
| 0x404 | 0x10 | 15:15 | DIS_RENWAY | |
| 0x404 | 0x10 | 14:14 | BYP_8B10B | |
| 0x404 | 0x10 | 13:12 | CDET | |
| 0x404 | 0x10 | 11:11 | DIS_TMR_CMA | |
| 0x404 | 0x10 | 10:10 | DIS_APX | |
| 0x404 | 0x10 | 09:09 | INV_HSI | |
| 0x404 | 0x10 | 08:08 | INV_HSO | |
| 0x404 | 0x10 | 07:06 | SDS_SDET_DEG | |
| 0x404 | 0x10 | 05:05 | CODEC_LPK | |
| 0x404 | 0x10 | 04:04 | AFE_LPK | |
| 0x404 | 0x10 | 03:03 | REMOTE_LPK | |
| 0x404 | 0x10 | 02:02 | SDS_TX_DOWN | |
| 0x404 | 0x10 | 01:01 | SDS_EN_RX | |
| 0x404 | 0x10 | 00:00 | SDS_EN_TX | |
| Page | Register | Bits | MAC SerDes 0 - page 3 | Absolute 0x2023 |
| 0x404 | 0x13 | 15:15 | WR_SOFT_RSTB | |
| 0x404 | 0x13 | 14:14 | USE_25M_CLK | |
| 0x404 | 0x13 | 13:13 | MARK_CARR_EXT | |
| 0x404 | 0x13 | 12:12 | SEL_DEG | |
| 0x404 | 0x13 | 11:08 | REG_CALIB_OK_CNT | |
| 0x404 | 0x13 | 07:07 | EXT_PWR_CTL | |
| 0x404 | 0x13 | 06:06 | SOFT_RST | Set to 1 then to 0 to run digital soft reset |
| 0x404 | 0x13 | 05:05 | CLR_SOFT_RSTB | |
| 0x404 | 0x13 | 04:00 | CMA_RQ | |
| Page | Register | Bits | MAC SerDes 0 - page 4 | Absolute 0x2024 |
| 0x404 | 0x14 | 15:13 | CFG_FRC_SDS_MODE | 0x6 = QSGMII |
| 0x404 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN | Enable SerDes forced mode |
| 0x404 | 0x14 | 11:08 | CFG_UPD_RXD | |
| 0x404 | 0x14 | 07:04 | CFG_UPD_TXD | |
| 0x404 | 0x14 | 03:03 | CFG_UPD_RXD_DYN | |
| 0x404 | 0x14 | 02:02 | CFG_EN_LINK_FIB1G | |
| 0x404 | 0x14 | 01:01 | CFG_EN_LINK_SGM | |
| 0x404 | 0x14 | 00:00 | CFG_SGM_CK_SEL | |
| Page | Register | Bits | MAC SerDes 0 - page 7 | Absolute 0x2027 |
| 0x404 | 0x17 | 15:15 | CFG_8B10B_NO_CREXT | |
| 0x404 | 0x17 | 14:14 | CFG_NEG_CLKWR_A2D | |
| 0x404 | 0x17 | 13:13 | CFG_MIIXF_TS1K | |
| 0x404 | 0x17 | 12:12 | CFG_DLY_PRE8 | |
| 0x404 | 0x17 | 11:11 | CFG_GRXD_SEL | |
| 0x404 | 0x17 | 10:10 | CFG_LPI_CMD_MII | |
| 0x404 | 0x17 | 09:09 | CFG_MARK_RXSCR_ERR | |
| 0x404 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR | |
| 0x404 | 0x17 | 07:04 | BYP_START | |
| 0x404 | 0x17 | 03:00 | BYP_END | |
| Page | Register | Bits | MAC SerDes 1 - page 0 | Absolute 0x2120 |
| 0x424 | 0x10 | 15:15 | DIS_RENWAY | |
| 0x424 | 0x10 | 14:14 | BYP_8B10B | |
| 0x424 | 0x10 | 13:12 | CDET | |
| 0x424 | 0x10 | 11:11 | DIS_TMR_CMA | |
| 0x424 | 0x10 | 10:10 | DIS_APX | |
| 0x424 | 0x10 | 09:09 | INV_HSI | |
| 0x424 | 0x10 | 08:08 | INV_HSO | |
| 0x424 | 0x10 | 07:06 | SDS_SDET_DEG | |
| 0x424 | 0x10 | 05:05 | CODEC_LPK | |
| 0x424 | 0x10 | 04:04 | AFE_LPK | |
| 0x424 | 0x10 | 03:03 | REMOTE_LPK | |
| 0x424 | 0x10 | 02:02 | SDS_TX_DOWN | |
| 0x424 | 0x10 | 01:01 | SDS_EN_RX | |
| 0x424 | 0x10 | 00:00 | SDS_EN_TX | |
| Page | Register | Bits | MAC SerDes 1 - page 3 | Absolute 0x2123 |
| 0x424 | 0x13 | 15:15 | WR_SOFT_RSTB | |
| 0x424 | 0x13 | 14:14 | USE_25M_CLK | |
| 0x424 | 0x13 | 13:13 | MARK_CARR_EXT | |
| 0x424 | 0x13 | 12:12 | SEL_DEG | |
| 0x424 | 0x13 | 11:08 | REG_CALIB_OK_CNT | |
| 0x424 | 0x13 | 07:07 | EXT_PWR_CTL | |
| 0x424 | 0x13 | 06:06 | SOFT_RST | |
| 0x424 | 0x13 | 05:05 | CLR_SOFT_RSTB | |
| 0x424 | 0x13 | 04:00 | CMA_RQ | |
| Page | Register | Bits | MAC SerDes 1 - page 4 | Absolute 0x2124 |
| 0x424 | 0x14 | 15:13 | CFG_FRC_SDS_MODE | |
| 0x424 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN | |
| 0x424 | 0x14 | 11:08 | CFG_UPD_RXD | |
| 0x424 | 0x14 | 07:04 | CFG_UPD_TXD | |
| 0x424 | 0x14 | 03:03 | CFG_UPD_RXD_DYN | |
| 0x424 | 0x14 | 02:02 | CFG_EN_LINK_FIB1G | |
| 0x424 | 0x14 | 01:01 | CFG_EN_LINK_SGM | |
| 0x424 | 0x14 | 00:00 | CFG_SGM_CK_SEL | |
| Page | Register | Bits | MAC SerDes 0 - page 7 | Absolute 0x2127 |
| 0x424 | 0x17 | 15:15 | CFG_8B10B_NO_CREXT | |
| 0x424 | 0x17 | 14:14 | CFG_NEG_CLKWR_A2D | |
| 0x424 | 0x17 | 13:13 | CFG_MIIXF_TS1K | |
| 0x424 | 0x17 | 12:12 | CFG_DLY_PRE8 | |
| 0x424 | 0x17 | 11:11 | CFG_GRXD_SEL | |
| 0x424 | 0x17 | 10:10 | CFG_LPI_CMD_MII | |
| 0x424 | 0x17 | 09:09 | CFG_MARK_RXSCR_ERR | |
| 0x424 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR | |
| 0x424 | 0x17 | 07:04 | BYP_START | |
| 0x424 | 0x17 | 03:00 | BYP_END | |
| Page | Register | Bits | Unknown CMU register | Absolute 0x233c |
| 0x467 | 0x14 | 15:0 | UNKNOWN | For CMU reset write 0x143d, 0x3c15, 0x3c17, 0x0000 |