mirror of
https://github.com/plappermaul/realtek-doc.git
synced 2025-12-10 07:44:41 +01:00
9.4 KiB
9.4 KiB
RTL8214FC/RTL8218B (maybe generic RTL821x) Register Layout
This is a sum up of what we got from the comments in the GPL sources. Additionally some SerDes registers where identified that work similar like the RTL838x/RTL839x built in SerDes.
These basic registers are organized in pages of 32. Each page knows registers 0x00-0x1F
| Page | Register | Bits | Feature | Documentation |
|---|---|---|---|---|
| Page | Register | Bits | INER | Interrupt enable register |
| 0xa42 | 0x12 | 04:04 | LINK_CHANGE_INT | |
| Page | Register | Bits | unknown | |
| 0xa42 | 0x14 | 07:07 | 500M_EEE_ABILITY | |
| Page | Register | Bits | PHYCR2 | |
| 0xa43 | 0x19 | 15:14 | RESERVED | |
| 0xa43 | 0x19 | 13:12 | CLOCKOUT_SOURCE | |
| 0xa43 | 0x19 | 11:11 | CLOCKOUT_FREQUENCY | |
| 0xa43 | 0x19 | 10:08 | RESERVED | |
| 0xa43 | 0x19 | 07:07 | CLOCKOUT_SSC_EN | |
| 0xa43 | 0x19 | 06:06 | CENTERTAP_SHORT_EN | |
| 0xa43 | 0x19 | 05:05 | PHY_MODE_EEE_EN | set to 1 to enable EEE |
| 0xa43 | 0x19 | 04:04 | RESERVED | |
| 0xa43 | 0x19 | 03:03 | SYSCLK_SSC_EN | |
| 0xa43 | 0x19 | 02:02 | RESERVED | |
| 0xa43 | 0x19 | 01:01 | RXC_EN | |
| 0xa43 | 0x19 | 00:00 | CLOCKOUT_EN | |
| Page | Register | Bits | SDS Indirect | SerDes Indirect Access |
| 0xa43 | 0x1B | 15:00 | PATCH_ADDRESS | patch step 3, 5, 7, .. write address |
| 0xa43 | 0x1C | 15:00 | PATCH_VALUE | patch step 4, 6, 8, ... read/write value |
| Page | Register | Bits | PHYCR3 | PHY specific control register 3 |
| 0xa44 | 0x11 | 09:09 | RETRY_DOWN_SPEED_500 | |
| 0xa44 | 0x11 | 05:05 | THR_RETRY_SPDN | 0 = 7 times, 1 = 3 times |
| 0xa44 | 0x11 | 03:03 | EN_RETRY_SPEED_DOW | |
| 0xa44 | 0x11 | 02:02 | 2PAIR_AUTO_DOWNSPEED | |
| Page | Register | Bits | unknown | |
| 0xb80 | 0x10 | 04:04 | PATCH_READY | patch step 2: wait until SerDEs acces ready (=1), go over to 0xa43:0x1b |
| Page | Register | Bits | unknown | |
| 0xb82 | 0x10 | 04:04 | ENABLE_PATCH | patch step 1: set to 1 to gain SerDEs access, go over to 0xb80:0x10 |
These additional/internal registers are organized in pages of 8. Each page knows registers 0x10-0x17. Their "absoulte" address can be calucalted by the formula page * 8 + (register - 16). It seems as if they are for the whole chip package and only accessed via the first port.
| Page | Register | Bits | Feature | Documentation |
|---|---|---|---|---|
| Page | Register | Bits | Unknown | Absolute 0x1308 |
| 0x261 | 0x10 | 14:13 | UNKOWN_RESET | write 0x3 and afterwards 0x0 |
| Page | Register | Bits | Unknown | Absolute 0x130b |
| 0x261 | 0x13 | 13:10 | DIS_FIBER_TX | each bit for on of ports 3-0 to disable (1) or enable (0) fiber tx |
| Page | Register | Bits | PTP feature | Absolute 0x1600 |
| 0x2C0 | 0x10 | 15:00 | PTP_TIME_NSEC_L | |
| 0x2C0 | 0x11 | 15:00 | PTP_TIME_NSEC_H | |
| 0x2C0 | 0x12 | 15:00 | PTP_TIME_SEC_L | |
| 0x2C0 | 0x13 | 15:00 | PTP_TIME_SEC_H | |
| 0x2C0 | 0x14 | 15:00 | PTP_TIME_CFG_0 | |
| 0x2C0 | 0x15 | 15:00 | PTP_OTAG_TPID | |
| 0x2C0 | 0x16 | 15:00 | PTP_ITAG_TPID | |
| 0x2C0 | 0x17 | 15:00 | PTP_MAC_ADDR_L | |
| 0x2C1 | 0x10 | 15:00 | PTP_MAC_ADDR_M | |
| 0x2C1 | 0x11 | 15:00 | PTP_MAC_ADDR_H | |
| 0x2C1 | 0x12 | 15:00 | PTP_TIME_NSEC_L_RO | |
| 0x2C1 | 0x13 | 15:00 | PTP_TIME_NSEC_H_RO | |
| 0x2C1 | 0x14 | 15:00 | PTP_TIME_SEC_L_RO | |
| 0x2C1 | 0x15 | 15:00 | PTP_TIME_SEC_H_RO | |
| 0x2C1 | 0x16 | 15:00 | PTP_TIME_CFG_1 | |
| 0x2C1 | 0x17 | 15:00 | PTP_TIME_INT_STS_P | |
| Page | Register | Bits | MAC SerDes 0 - register 0 | Absolute 0x2020 |
| 0x404 | 0x10 | 15:15 | DIS_RENWAY | |
| 0x404 | 0x10 | 14:14 | BYP_8B10B | |
| 0x404 | 0x10 | 13:12 | CDET | |
| 0x404 | 0x10 | 11:11 | DIS_TMR_CMA | |
| 0x404 | 0x10 | 10:10 | DIS_APX | |
| 0x404 | 0x10 | 09:09 | INV_HSI | |
| 0x404 | 0x10 | 08:08 | INV_HSO | |
| 0x404 | 0x10 | 07:06 | SDS_SDET_DEG | |
| 0x404 | 0x10 | 05:05 | CODEC_LPK | |
| 0x404 | 0x10 | 04:04 | AFE_LPK | |
| 0x404 | 0x10 | 03:03 | REMOTE_LPK | |
| 0x404 | 0x10 | 02:02 | SDS_TX_DOWN | |
| 0x404 | 0x10 | 01:01 | SDS_EN_RX | |
| 0x404 | 0x10 | 00:00 | SDS_EN_TX | |
| Page | Register | Bits | MAC SerDes 0 - register 3 | Absolute 0x2023 |
| 0x404 | 0x13 | 15:15 | WR_SOFT_RSTB | |
| 0x404 | 0x13 | 14:14 | USE_25M_CLK | |
| 0x404 | 0x13 | 13:13 | MARK_CARR_EXT | |
| 0x404 | 0x13 | 12:12 | SEL_DEG | |
| 0x404 | 0x13 | 11:08 | REG_CALIB_OK_CNT | |
| 0x404 | 0x13 | 07:07 | EXT_PWR_CTL | |
| 0x404 | 0x13 | 06:06 | SOFT_RST | Set to 1 then to 0 to run digital soft reset |
| 0x404 | 0x13 | 05:05 | CLR_SOFT_RSTB | |
| 0x404 | 0x13 | 04:00 | CMA_RQ | |
| Page | Register | Bits | MAC SerDes 0 - register 4 | Absolute 0x2024 |
| 0x404 | 0x14 | 15:13 | CFG_FRC_SDS_MODE | 0x6 = QSGMII |
| 0x404 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN | Enable SerDes forced mode |
| 0x404 | 0x14 | 11:08 | CFG_UPD_RXD | |
| 0x404 | 0x14 | 07:04 | CFG_UPD_TXD | |
| 0x404 | 0x14 | 03:03 | CFG_UPD_RXD_DYN | |
| 0x404 | 0x14 | 02:02 | CFG_EN_LINK_FIB1G | |
| 0x404 | 0x14 | 01:01 | CFG_EN_LINK_SGM | |
| 0x404 | 0x14 | 00:00 | CFG_SGM_CK_SEL | |
| Page | Register | Bits | MAC SerDes 0 - register 7 | Absolute 0x2027 |
| 0x404 | 0x17 | 15:15 | CFG_8B10B_NO_CREXT | |
| 0x404 | 0x17 | 14:14 | CFG_NEG_CLKWR_A2D | |
| 0x404 | 0x17 | 13:13 | CFG_MIIXF_TS1K | |
| 0x404 | 0x17 | 12:12 | CFG_DLY_PRE8 | |
| 0x404 | 0x17 | 11:11 | CFG_GRXD_SEL | |
| 0x404 | 0x17 | 10:10 | CFG_LPI_CMD_MII | |
| 0x404 | 0x17 | 09:09 | CFG_MARK_RXSCR_ERR | |
| 0x404 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR | |
| 0x404 | 0x17 | 07:04 | BYP_START | |
| 0x404 | 0x17 | 03:00 | BYP_END | |
| Page | Register | Bits | MAC SerDes 0 - register 12 | Absolute 0x202c |
| 0x405 | 0x14 | 15:08 | CFG_INB_TIMEOUT | |
| 0x405 | 0x14 | 07:04 | ABILITY | |
| 0x405 | 0x14 | 03:03 | RDM_ALGOR | Redundancy algorithm 0 = 16/20b, 1 = 32/40b |
| 0x405 | 0x14 | 02:02 | SD_DET_ALGOR | |
| 0x405 | 0x14 | 01:01 | AUTO_DET_ALGOR | |
| 0x405 | 0x14 | 00:00 | SEND_NP_ON | |
| Page | Register | Bits | MAC SerDes 0 - page unknown | Absolute 0x2060 |
| 0x40c | 0x11 | 15:00 | This is some unknown PLL register - write 0x4000 to disable ring PLL | |
| Page | Register | Bits | MAC SerDes 1 - register 0 | Absolute 0x2120 |
| 0x424 | 0x10 | 15:15 | DIS_RENWAY | |
| 0x424 | 0x10 | 14:14 | BYP_8B10B | |
| 0x424 | 0x10 | 13:12 | CDET | |
| 0x424 | 0x10 | 11:11 | DIS_TMR_CMA | |
| 0x424 | 0x10 | 10:10 | DIS_APX | |
| 0x424 | 0x10 | 09:09 | INV_HSI | |
| 0x424 | 0x10 | 08:08 | INV_HSO | |
| 0x424 | 0x10 | 07:06 | SDS_SDET_DEG | |
| 0x424 | 0x10 | 05:05 | CODEC_LPK | |
| 0x424 | 0x10 | 04:04 | AFE_LPK | |
| 0x424 | 0x10 | 03:03 | REMOTE_LPK | |
| 0x424 | 0x10 | 02:02 | SDS_TX_DOWN | |
| 0x424 | 0x10 | 01:01 | SDS_EN_RX | |
| 0x424 | 0x10 | 00:00 | SDS_EN_TX | |
| Page | Register | Bits | MAC SerDes 1 - register 3 | Absolute 0x2123 |
| 0x424 | 0x13 | 15:15 | WR_SOFT_RSTB | |
| 0x424 | 0x13 | 14:14 | USE_25M_CLK | |
| 0x424 | 0x13 | 13:13 | MARK_CARR_EXT | |
| 0x424 | 0x13 | 12:12 | SEL_DEG | |
| 0x424 | 0x13 | 11:08 | REG_CALIB_OK_CNT | |
| 0x424 | 0x13 | 07:07 | EXT_PWR_CTL | |
| 0x424 | 0x13 | 06:06 | SOFT_RST | |
| 0x424 | 0x13 | 05:05 | CLR_SOFT_RSTB | |
| 0x424 | 0x13 | 04:00 | CMA_RQ | |
| Page | Register | Bits | MAC SerDes 1 - register 4 | Absolute 0x2124 |
| 0x424 | 0x14 | 15:13 | CFG_FRC_SDS_MODE | |
| 0x424 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN | |
| 0x424 | 0x14 | 11:08 | CFG_UPD_RXD | |
| 0x424 | 0x14 | 07:04 | CFG_UPD_TXD | |
| 0x424 | 0x14 | 03:03 | CFG_UPD_RXD_DYN | |
| 0x424 | 0x14 | 02:02 | CFG_EN_LINK_FIB1G | |
| 0x424 | 0x14 | 01:01 | CFG_EN_LINK_SGM | |
| 0x424 | 0x14 | 00:00 | CFG_SGM_CK_SEL | |
| Page | Register | Bits | MAC SerDes 1 - register 7 | Absolute 0x2127 |
| 0x424 | 0x17 | 15:15 | CFG_8B10B_NO_CREXT | |
| 0x424 | 0x17 | 14:14 | CFG_NEG_CLKWR_A2D | |
| 0x424 | 0x17 | 13:13 | CFG_MIIXF_TS1K | |
| 0x424 | 0x17 | 12:12 | CFG_DLY_PRE8 | |
| 0x424 | 0x17 | 11:11 | CFG_GRXD_SEL | |
| 0x424 | 0x17 | 10:10 | CFG_LPI_CMD_MII | |
| 0x424 | 0x17 | 09:09 | CFG_MARK_RXSCR_ERR | |
| 0x424 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR | |
| 0x424 | 0x17 | 07:04 | BYP_START | |
| 0x424 | 0x17 | 03:00 | BYP_END | |
| Page | Register | Bits | MAC SerDes 1 - register 12 | Absolute 0x212c |
| 0x425 | 0x14 | 15:08 | CFG_INB_TIMEOUT | |
| 0x425 | 0x14 | 07:04 | ABILITY | |
| 0x425 | 0x14 | 03:03 | RDM_ALGOR | Redundancy algorithm 0 = 16/20b, 1 = 32/40b |
| 0x425 | 0x14 | 02:02 | SD_DET_ALGOR | |
| 0x425 | 0x14 | 01:01 | AUTO_DET_ALGOR | |
| 0x425 | 0x14 | 00:00 | SEND_NP_ON | |
| Page | Register | Bits | MAC SerDes 1 - page unknown | Absolute 0x2161 |
| 0x42c | 0x11 | 15:00 | This is some unknown PLL register - write 0x4000 to disable ring PLL | |
| Page | Register | Bits | MAC SerDes 1 - page unknown | Absolute 0x2162 |
| 0x42c | 0x12 | 15:00 | ||
| Page | Register | Bits | MAC SerDes 1 - page unknown | Absolute 0x2169 |
| 0x42d | 0x11 | 00:00 | ANA_RESET | |
| Page | Register | Bits | MAC SerDes 1 - page unknown | Absolute 0x2171 |
| 0x42e | 0x11 | 15:00 | ||
| Page | Register | Bits | Unknown SerDes - page unknown | Absolute 0x2261 |
| 0x44c | 0x11 | 15:00 | This is some unknown PLL register - write 0x4000 to disable ring PLL | |
| Page | Register | Bits | Unknown filter register | Absolute 0x2310 |
| 0x462 | 0x10 | 13:12 | OFFSET_CALIBRATION | |
| Page | Register | Bits | Unknown filter register 1 | Absolute 0x2322 |
| 0x464 | 0x12 | 15:11 | FILTER_0 | |
| 0x464 | 0x12 | 10:07 | FORCE | |
| Page | Register | Bits | Unknown filter register 2 | Absolute 0x2323 |
| 0x464 | 0x13 | 14:10 | FILTER_3 | |
| 0x464 | 0x13 | 09:05 | FILTER_2 | |
| 0x464 | 0x13 | 04:00 | FILTER_1 | |
| Page | Register | Bits | Unknown | Absolute 0x2327 |
| 0x464 | 0x17 | 15:15 | UNKNOWN_RESET | write 1 and 0 to do some reset |
| Page | Register | Bits | Unknown CMU register | Absolute 0x233c |
| 0x467 | 0x14 | 15:0 | For CMU reset write 0x143d, 0x3c15, 0x3c17, 0x0000 |