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@ -23,18 +23,18 @@ Page | Register | Bits | Feature | Documentation
0xa43 | 0x19 | 02:02 | RESERVED
0xa43 | 0x19 | 01:01 | RXC_EN
0xa43 | 0x19 | 00:00 | CLOCKOUT_EN
**Page** | **Register** | **Bits** | **PATCH** | **patch registers**
0xa43 | 0x1B | 15:00 | PATCH_ADDRESS | patch step 3, 5, 7, .. write address to be patched
0xa43 | 0x1C | 15:00 | PATCH_VALUE | patch step 4, 6, 8, ... write value to be patched at address
**Page** | **Register** | **Bits** | **SDS Indirect** | **SerDes Indirect Access**
0xa43 | 0x1B | 15:00 | PATCH_ADDRESS | patch step 3, 5, 7, .. write address
0xa43 | 0x1C | 15:00 | PATCH_VALUE | patch step 4, 6, 8, ... read/write value
**Page** | **Register** | **Bits** | **PHYCR3** | **PHY specific control register 3**
0xa44 | 0x11 | 09:09 | RETRY_DOWN_SPEED_500
0xa44 | 0x11 | 05:05 | THR_RETRY_SPDN | 0 = 7 times, 1 = 3 times
0xa44 | 0x11 | 03:03 | EN_RETRY_SPEED_DOW
0xa44 | 0x11 | 02:02 | 2PAIR_AUTO_DOWNSPEED
**Page** | **Register** | **Bits** | **unknown** |
0xb80 | 0x10 | 04:04 | PATCH_READY | patch step 2: wait for 1 to start patching, go over to 0xa43:0x1b
0xb80 | 0x10 | 04:04 | PATCH_READY | patch step 2: wait until SerDEs acces ready (=1), go over to 0xa43:0x1b
**Page** | **Register** | **Bits** | **unknown** |
0xb82 | 0x10 | 04:04 | ENABLE_PATCH | patch step 1: set to 1 to start, go over to 0xb80:0x10
0xb82 | 0x10 | 04:04 | ENABLE_PATCH | patch step 1: set to 1 to gain SerDEs access, go over to 0xb80:0x10
These additional/internal registers are organized in pages of 8. Each page knows registers 0x10-0x17. Their "absoulte" address can be calucalted by the formula page * 8 + (register - 16). It seems as if they are for the whole chip package and only accessed via the first port.