mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2026-02-19 15:51:15 +01:00
Regardless of the number of receive queues (8 or 32) the interrupt status and mask registers are built up bitwise in the same way: - 8/32 rx run out interrupts - 8/32 rx done interrupts - 2 tx tone interrupts - 2 tx all done interrupts - 3 L2 notify interrupts (only RTL839x) So one can always derive the bit position of those fields by using the device specific rx_rings configuration setting. To simplify the code these registers will be handled by central helpers in the future. In a first step provide a interrupt base register definition that points to the first interrupt type - aka the rx run out interrupts. To not overcomplicate things simply reuse the existing DMA_IF_INTR_MSK and DMA_IF_INTR_STS naming convention. Until all gets fixed the runout registers on RTL93xx will be accessible by that name. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/21893 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
||
|---|---|---|
| .. | ||
| airoha | ||
| apm821xx | ||
| armsr | ||
| at91 | ||
| ath79 | ||
| bcm27xx | ||
| bcm47xx | ||
| bcm53xx | ||
| bcm4908 | ||
| bmips | ||
| d1 | ||
| econet | ||
| gemini | ||
| generic | ||
| imx | ||
| ipq40xx | ||
| ipq806x | ||
| ixp4xx | ||
| kirkwood | ||
| lantiq | ||
| layerscape | ||
| loongarch64 | ||
| malta | ||
| mediatek | ||
| microchipsw | ||
| mpc85xx | ||
| mvebu | ||
| mxs | ||
| octeon | ||
| omap | ||
| pistachio | ||
| qoriq | ||
| qualcommax | ||
| qualcommbe | ||
| ramips | ||
| realtek | ||
| rockchip | ||
| sifiveu | ||
| siflower | ||
| starfive | ||
| stm32 | ||
| sunxi | ||
| tegra | ||
| uml | ||
| x86 | ||
| zynq | ||
| Makefile | ||