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mpc85xx: p2020: add support for WatchGuard XTM330 (NC5AE7)
Hardware specifications:
- CPU: Freescale/NXP P2020, dual-core PowerPC @ 1 GHz
- RAM: 1 GB DDR3
- Flash: 2 MB NOR, 512 MB NAND
- Networking: 7x Gigabit Ethernet ports (via two Marvell 88E6171
switches, each attached to a different MAC)
- USB: 2x USB 2.0 ports (front panel)
- mini-PCIe slot
- RTC: Ricoh RS5C372A
- 4 buttons (via external MCU)
- 3 LEDs (via external MCU)
- LCD display (via external MCU)
Installation procedure:
1. Obtain the original MAC address table from the stock bootlog, for
example:
setting device eth0 to 00:90:7f:00:00:01
setting device eth1 to 00:90:7f:00:00:02
setting device eth2 to 00:90:7f:00:00:03
setting device eth3 to 00:90:7f:00:00:04
setting device eth4 to 00:90:7f:00:00:05
setting device eth5 to 00:90:7f:00:00:06
setting device eth6 to 00:90:7f:00:00:07
2. Open the case and move jumper JP1 from 2-3 to 1-2 to enter FAILSAFE
mode.
3. Power on the device and interrupt the boot process to access the U-Boot
shell.
4. Program the MAC base address into the EEPROM (text after '#' is a
comment):
mac ports 3
mac 2 00:90:7f:00:00:01 # first MAC address from bootlog
mac save
5. Reset the device and enter the U-Boot console again.
6. Connect a TFTP server to port 6 and boot the initramfs image:
setenv ipaddr 192.168.1.3
setenv serverip 192.168.1.2
setenv loadaddr 1000000
tftpboot $loadaddr openwrt-mpc85xx-p2020-watchguard_xtm330-initramfs-kernel.bin
bootm $loadaddr
7. (Optional) Backup all MTD partitions if you want the ability to restore
stock firmware.
8. Perform a normal sysupgrade from the initramfs environment.
9. Power off the device and move jumper JP1 back to 2-3.
10. The device will now boot OpenWrt.
Known issues:
- LCD, buttons and LEDs are controlled by an external MCU; the protocol is
currently unknown.
- The internal connection between the two Marvell switches is unused by
OpenWrt.
- The stock firmware uses an empty U-Boot environment; saving variables
modifies the environment and prevents a normal boot. FAILSAFE U-Boot
remains functional.
- WatchGuard configuration is encrypted; DSA MAC addresses are stored in
this configuration.
- Failsafe Ethernet works on port1.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21020
(cherry picked from commit 6150f9ceab)
Link: https://github.com/openwrt/openwrt/pull/21517
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Pawel Dembicki
Hauke Mehrtens
parent
c9e2d8191b
commit
85a4358432
9 changed files with 415 additions and 3 deletions
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@ -24,6 +24,9 @@ watchguard,firebox-t10|\
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watchguard,firebox-t15)
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ubootenv_add_uci_config "$(find_mtd_part 'u-boot-env')" "0x0" "0x2000" "0x10000"
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;;
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watchguard,xtm330)
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ubootenv_add_uci_config "/dev/mtd4" "0x0" "0x10000" "0x10000"
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;;
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aerohive,hiveap-330)
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ubootenv_add_uci_config "$(find_mtd_part 'u-boot-env')" "0x0" "0x20000" "0x10000"
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;;
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@ -33,6 +33,9 @@ watchguard,firebox-t10|\
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watchguard,firebox-t15)
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ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0"
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;;
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watchguard,xtm330)
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ucidef_set_interfaces_lan_wan "port1 port2 port3 port4 port5 port6" "port0"
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;;
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*)
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ucidef_set_interfaces_lan_wan "eth0" "eth1"
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;;
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@ -3,7 +3,14 @@
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#
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mpc85xx_set_preinit_iface() {
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ifname=eth0
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case $(board_name) in
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watchguard,xtm330)
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ifname=port1
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;;
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*)
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ifname=eth0
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;;
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esac
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}
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boot_hook_add preinit_main mpc85xx_set_preinit_iface
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@ -17,7 +17,8 @@ platform_do_upgrade() {
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ocedo,panda|\
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sophos,red-15w-rev1|\
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watchguard,firebox-t10|\
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watchguard,firebox-t15)
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watchguard,firebox-t15|\
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watchguard,xtm330)
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nand_do_upgrade "$1"
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;;
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*)
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362
target/linux/mpc85xx/files/arch/powerpc/boot/dts/xtm330.dts
Normal file
362
target/linux/mpc85xx/files/arch/powerpc/boot/dts/xtm330.dts
Normal file
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@ -0,0 +1,362 @@
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// SPDX-License-Identifier: GPL-2.0-or-later or MIT
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/*
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* WatchGuard XTM 330 (NC5AE7) Device Tree Source File
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*
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* Copyright (C) 2025 Pawel Dembicki <paweldembicki@gmail.com>
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*/
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/dts-v1/;
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/include/ "fsl/p2020si-pre.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "WatchGuard XTM 330 (NC5AE7)";
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compatible = "watchguard,xtm330";
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet2;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci2;
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};
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chosen {
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bootargs-override = "console=ttyS0,115200";
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};
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memory {
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device_type = "memory";
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};
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lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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/* NOR and NAND Flashes */
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ranges = < 0x0 0x0 0x0 0xefe00000 0x00200000
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0x1 0x0 0x0 0xffa00000 0x00040000 >;
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nor@0,0 {
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x200000>;
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bank-width = <2>;
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device-width = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "cfg0";
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reg = <0x00000000 0x00020000>;
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};
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partition@20000 {
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label = "cfg1";
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reg = <0x00020000 0x00010000>;
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};
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partition@30000 {
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label = "mfg-data";
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reg = <0x00030000 0x00010000>;
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};
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partition@40000 {
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label = "bootopt";
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reg = <0x00040000 0x000b0000>;
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};
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partition@f0000 {
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label = "u-boot-env";
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reg = <0x000f0000 0x00010000>;
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};
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partition@100000 {
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label = "u-boot";
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reg = <0x00100000 0x00080000>;
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};
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partition@180000 {
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label = "u-boot-failsafe";
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reg = <0x00180000 0x00080000>;
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};
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};
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand";
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reg = <0x1 0x0 0x40000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "dtb";
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reg = <0x00000000 0x00020000>;
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};
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partition@20000 {
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label = "kernel";
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reg = <0x00020000 0x00500000>;
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};
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partition@520000 {
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label = "ubi";
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reg = <0x00520000 0x1fae0000>;
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};
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};
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};
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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gpio0: gpio-controller@fc00 {
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usb-hub-reset-hog {
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gpio-hog;
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gpios = <12 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "usb-hub-reset";
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};
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};
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i2c@3000 {
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rtc@32 {
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compatible = "ricoh,rs5c372a";
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reg = <0x32>;
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};
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hwmon@2d {
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compatible = "winbond,w83793";
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reg = <0x2d>;
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};
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eeprom@54 {
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compatible = "atmel,24c04";
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reg = <0x54>;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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mac_addr_0: macaddr@0 {
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compatible = "mac-base";
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reg = <0x4e 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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};
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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mdio@24520 {
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switch@10 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10>;
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dsa,member = <0 0>;
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reset-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "port0";
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nvmem-cells = <&mac_addr_0 0>;
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nvmem-cell-names = "mac-address";
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};
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port@1 {
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reg = <1>;
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label = "port1";
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nvmem-cells = <&mac_addr_0 1>;
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nvmem-cell-names = "mac-address";
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};
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port@2 {
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reg = <2>;
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label = "port2";
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nvmem-cells = <&mac_addr_0 2>;
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nvmem-cell-names = "mac-address";
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};
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port@3 {
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reg = <3>;
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label = "port3";
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nvmem-cells = <&mac_addr_0 3>;
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nvmem-cell-names = "mac-address";
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};
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port@4 {
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reg = <4>;
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label = "internal1";
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};
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port@5 {
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reg = <5>;
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phy-mode = "rgmii-id";
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ethernet = <&enet2>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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switch@11 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x11>;
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dsa,member = <1 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "internal2";
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};
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port@1 {
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reg = <1>;
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label = "port4";
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nvmem-cells = <&mac_addr_0 4>;
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nvmem-cell-names = "mac-address";
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};
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port@2 {
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reg = <2>;
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label = "port5";
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nvmem-cells = <&mac_addr_0 5>;
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nvmem-cell-names = "mac-address";
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};
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port@3 {
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reg = <3>;
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label = "port6";
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nvmem-cells = <&mac_addr_0 6>;
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nvmem-cell-names = "mac-address";
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};
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port@5 {
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reg = <5>;
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phy-mode = "rgmii-id";
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ethernet = <&enet0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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mdio@25520 {
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status = "disabled";
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};
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mdio@26520 {
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status = "disabled";
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};
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enet0: ethernet@24000 {
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phy-connection-type = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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enet1: ethernet@25000 {
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status = "disabled";
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};
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enet2: ethernet@26000 {
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phy-connection-type = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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pci0: pcie@ffe08000 {
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reg = <0 0xffe08000 0 0x1000>;
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ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
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status = "disabled";
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pcie@0 {
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ranges = < 0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe09000 {
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reg = <0 0xffe09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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status = "disabled";
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pcie@0 {
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ranges = < 0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci2: pcie@ffe0a000 {
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reg = <0 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = < 0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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};
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/include/ "fsl/p2020si-post.dtsi"
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@ -3,7 +3,7 @@ define Device/freescale_p2020rdb
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DEVICE_MODEL := P2020RDB
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DEVICE_DTS_DIR := $(DTS_DIR)/fsl
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DEVICE_PACKAGES := kmod-hwmon-lm90 kmod-rtc-ds1307 \
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kmod-gpio-pca953x kmod-eeprom-at24
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kmod-gpio-pca953x
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BLOCKSIZE := 128k
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KERNEL := kernel-bin | gzip | \
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fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
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@ -13,3 +13,19 @@ define Device/freescale_p2020rdb
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pad-rootfs $$(BLOCKSIZE) | append-metadata
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endef
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TARGET_DEVICES += freescale_p2020rdb
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define Device/watchguard_xtm330
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DEVICE_VENDOR := WatchGuard
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DEVICE_MODEL := XTM 330
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DEVICE_VARIANT := NC5AE7
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DEVICE_PACKAGES := kmod-dsa-mv88e6xxx kmod-hwmon-w83793 \
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kmod-rtc-rs5c372a
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BLOCKSIZE := 128k
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KERNEL = kernel-bin | fit none $(KDIR)/image-$$(DEVICE_DTS).dtb
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KERNEL_NAME := zImage.la3000000
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KERNEL_ENTRY := 0x3000000
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KERNEL_LOADADDR := 0x3000000
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IMAGES := sysupgrade.bin
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IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
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endef
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TARGET_DEVICES += watchguard_xtm330
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@ -1,8 +1,10 @@
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CONFIG_BLK_DEV_NVME=y
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CONFIG_CONTEXT_TRACKING=y
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CONFIG_CONTEXT_TRACKING_IDLE=y
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CONFIG_CMDLINE_OVERRIDE=y
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CONFIG_CPU_RMAP=y
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CONFIG_DEFAULT_UIMAGE=y
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CONFIG_EEPROM_AT24=y
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CONFIG_FSL_ULI1575=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_IRQ_MIGRATION=y
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@ -16,10 +18,15 @@ CONFIG_MTD_CFI=y
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CONFIG_MTD_NAND_FSL_ELBC=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_SPLIT_FIT_FW=y
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CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
CONFIG_PADATA=y
|
||||
|
|
@ -29,6 +36,7 @@ CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
|||
CONFIG_PPC_I8259=y
|
||||
CONFIG_PPC_MSI_BITMAP=y
|
||||
CONFIG_PPC_P2020=y
|
||||
CONFIG_PPC_ZIMAGE_LA3000000=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
|
|
@ -42,4 +50,5 @@ CONFIG_TARGET_CPU="8540"
|
|||
CONFIG_TARGET_CPU_BOOL=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_XPS=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
BOARDNAME:=P2020
|
||||
KERNEL_IMAGES:=zImage.la3000000
|
||||
|
||||
define Target/Description
|
||||
Build firmware images for Freescale P2020 based boards.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,10 @@
|
|||
--- a/arch/powerpc/platforms/85xx/Kconfig
|
||||
+++ b/arch/powerpc/platforms/85xx/Kconfig
|
||||
@@ -187,6 +187,7 @@ config PPC_P2020
|
||||
default y if MPC85xx_DS || MPC85xx_RDB
|
||||
select DEFAULT_UIMAGE
|
||||
select SWIOTLB
|
||||
+ select PPC_ZIMAGE_LA3000000
|
||||
imply PPC_I8259
|
||||
imply FSL_ULI1575 if PCI
|
||||
help
|
||||
Loading…
Add table
Reference in a new issue