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realtek: dsa: remove storm control
Commit78bf3a5f44("realtek: dsa: Fix rate control initialization") enabled code setting up the "storm control" feature. This casued a speed regression on rtl838x, reducing the effective max speed per port from line rate to around 500 Mbits/s. Storm control is a policy feature with a number of input parameters depending on use case and environment. It is not possible to define a meaningful static policy in the driver. The problem isn't just the arbitrary limits in the current code. Such features require userspace interfaces. Drop this code for now. It wasn't missed while it was disabled. Cc: Sven Eckelmann <se@simonwunderlich.de> Fixes:78bf3a5f44("realtek: dsa: Fix rate control initialization") Link: https://github.com/openwrt/openwrt/issues/21692 Signed-off-by: Bjørn Mork <bjorn@mork.no> Link: https://github.com/openwrt/openwrt/pull/21877 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Bjørn Mork
Robert Marko
parent
483d2f1756
commit
3972aeaf7c
2 changed files with 2 additions and 191 deletions
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@ -42,15 +42,6 @@ static void rtl839x_read_out_q_table(int port)
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rtl839x_exec_tbl2_cmd(cmd);
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}
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static void rtl838x_storm_enable(struct rtl838x_switch_priv *priv, int port, bool enable)
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{
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/* Enable Storm control for that port for UC, MC, and BC */
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if (enable)
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sw_w32(0x7, RTL838X_STORM_CTRL_LB_CTRL(port));
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else
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sw_w32(0x0, RTL838X_STORM_CTRL_LB_CTRL(port));
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}
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u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port)
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{
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if (port > priv->cpu_port)
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@ -73,67 +64,6 @@ int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate
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return old_rate;
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}
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/* Set the rate limit for a particular queue in Bits/s
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* units of the rate is 16Kbps
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*/
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void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,
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int queue, u32 rate)
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{
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if (port > priv->cpu_port)
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return;
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if (queue > 7)
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return;
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sw_w32(rate, RTL838X_SCHED_Q_EGR_RATE_CTRL(port, queue));
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}
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static void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv)
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{
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pr_info("Enabling Storm control\n");
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/* TICK_PERIOD_PPS */
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if (priv->id == 0x8380)
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sw_w32_mask(0x3ff << 20, 434 << 20, RTL838X_SCHED_LB_TICK_TKN_CTRL_0);
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/* Set burst rate */
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sw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); /* UC */
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sw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); /* MC and BC */
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/* Set burst Packets per Second to 32 */
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sw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); /* UC */
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sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); /* MC and BC */
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/* Include IFG in storm control, rate based on bytes/s (0 = packets) */
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sw_w32_mask(0, 1 << 6 | 1 << 5, RTL838X_STORM_CTRL);
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/* Bandwidth control includes preamble and IFG (10 Bytes) */
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sw_w32_mask(0, 1, RTL838X_SCHED_CTRL);
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/* On SoCs except RTL8382M, set burst size of port egress */
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if (priv->id != 0x8382)
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sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR);
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/* Enable storm control on all ports with a PHY and limit rates,
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* for UC and MC for both known and unknown addresses
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*/
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for (int i = 0; i < priv->cpu_port; i++) {
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if (priv->ports[i].phy) {
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sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i));
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sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i));
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sw_w32(0x8000, RTL838X_STORM_CTRL_PORT_BC(i));
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rtl838x_storm_enable(priv, i, true);
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}
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}
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/* Attack prevention, enable all attack prevention measures */
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/* sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL); */
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/* Attack prevention, drop (bit = 0) problematic packets on all ports.
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* Setting bit = 1 means: trap to CPU
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*/
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/* sw_w32(0, RTL838X_ATK_PRVNT_ACT); */
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/* Enable attack prevention on all ports */
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/* sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN); */
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}
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/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */
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u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port)
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{
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@ -182,110 +112,6 @@ int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate
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return old_rate;
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}
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/* Set the rate limit for a particular queue in Bits/s
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* units of the rate is 16Kbps
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*/
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static void rtl839x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,
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int queue, u32 rate)
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{
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int lsb = 128 + queue * 20;
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int low_byte = 8 - (lsb >> 5);
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int start_bit = lsb - (low_byte << 5);
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u32 high_mask = 0xfffff >> (32 - start_bit);
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pr_debug("%s: Setting egress rate on port %d, queue %d to %d\n",
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__func__, port, queue, rate);
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if (port >= priv->cpu_port)
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return;
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if (queue > 7)
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return;
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mutex_lock(&priv->reg_mutex);
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rtl839x_read_scheduling_table(port);
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sw_w32_mask(0xfffff << start_bit, (rate & 0xfffff) << start_bit,
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RTL839X_TBL_ACCESS_DATA_2(low_byte));
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if (high_mask)
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sw_w32_mask(high_mask, (rate & 0xfffff) >> (32 - start_bit),
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RTL839X_TBL_ACCESS_DATA_2(low_byte - 1));
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rtl839x_write_scheduling_table(port);
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mutex_unlock(&priv->reg_mutex);
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}
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static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv)
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{
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pr_info("%s: enabling rate control\n", __func__);
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/* Tick length and token size settings for SoC with 250MHz,
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* RTL8350 family would use 50MHz
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*/
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/* Set the special tick period */
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sw_w32(976563, RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL);
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/* Ingress tick period and token length 10G */
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sw_w32(18 << 11 | 151, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0);
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/* Ingress tick period and token length 1G */
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sw_w32(245 << 11 | 129, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1);
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/* Egress tick period 10G, bytes/token 10G and tick period 1G, bytes/token 1G */
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sw_w32(18 << 24 | 151 << 16 | 185 << 8 | 97, RTL839X_SCHED_LB_TICK_TKN_CTRL);
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/* Set the tick period of the CPU and the Token Len */
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sw_w32(3815 << 8 | 1, RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL);
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/* Set the Weighted Fair Queueing burst size */
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sw_w32_mask(0xffff, 4500, RTL839X_SCHED_LB_THR);
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/* Storm-rate calculation is based on bytes/sec (bit 5), include IFG (bit 6) */
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sw_w32_mask(0, 1 << 5 | 1 << 6, RTL839X_STORM_CTRL);
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/* Based on the rate control mode being bytes/s
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* set tick period and token length for 10G
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*/
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sw_w32(18 << 10 | 151, RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0);
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/* and for 1G ports */
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sw_w32(246 << 10 | 129, RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1);
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/* Set default burst rates on all ports (the same for 1G / 10G) with a PHY
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* for UC, MC and BC
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* For 1G port, the minimum burst rate is 1700, maximum 65535,
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* For 10G ports it is 2650 and 1048575 respectively
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*/
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for (int p = 0; p < priv->cpu_port; p++) {
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if (priv->ports[p].phy && !priv->ports[p].is10G) {
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sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_UC_1(p));
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sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_MC_1(p));
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sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_BC_1(p));
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}
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}
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/* Setup ingress/egress per-port rate control */
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for (int p = 0; p < priv->cpu_port; p++) {
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if (!priv->ports[p].phy)
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continue;
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if (priv->ports[p].is10G)
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rtl839x_set_egress_rate(priv, p, 625000); /* 10GB/s */
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else
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rtl839x_set_egress_rate(priv, p, 62500); /* 1GB/s */
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/* Setup queues: all RTL83XX SoCs have 8 queues, maximum rate */
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for (int q = 0; q < 8; q++)
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rtl839x_egress_rate_queue_limit(priv, p, q, 0xfffff);
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if (priv->ports[p].is10G) {
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/* Set high threshold to maximum */
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sw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p));
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} else {
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/* Set high threshold to maximum */
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sw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_1(p));
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}
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}
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/* Set global ingress low watermark rate */
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sw_w32(65532, RTL839X_IGR_BWCTRL_CTRL_LB_THR);
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}
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static void rtl838x_setup_prio2queue_matrix(int *min_queues)
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{
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u32 v = 0;
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@ -443,7 +269,7 @@ static void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *pri
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mutex_unlock(&priv->reg_mutex);
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}
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static void rtl838x_config_qos(struct rtl838x_switch_priv *priv)
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void rtldsa_838x_qos_init(struct rtl838x_switch_priv *priv)
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{
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u32 v;
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@ -488,7 +314,7 @@ static void rtl838x_config_qos(struct rtl838x_switch_priv *priv)
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sw_w32_mask(0, 7, RTL838X_QM_PKT2CPU_INTPRI_1);
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}
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static void rtl839x_config_qos(struct rtl838x_switch_priv *priv)
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void rtldsa_839x_qos_init(struct rtl838x_switch_priv *priv)
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{
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u32 v;
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@ -543,15 +369,3 @@ static void rtl839x_config_qos(struct rtl838x_switch_priv *priv)
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sw_w32(255 << 24 | 70 << 12 | 60, RTL839X_WRED_QUEUE_THR_CTRL(q, 0));
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}
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}
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void rtldsa_838x_qos_init(struct rtl838x_switch_priv *priv)
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{
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rtl838x_config_qos(priv);
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rtl838x_rate_control_init(priv);
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}
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void rtldsa_839x_qos_init(struct rtl838x_switch_priv *priv)
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{
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rtl839x_config_qos(priv);
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rtl839x_rate_control_init(priv);
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}
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@ -188,9 +188,6 @@ int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port);
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* collect them in this section.
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*/
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void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,
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int queue, u32 rate);
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void rtl839x_pie_rule_dump(struct pie_rule *pr);
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void rtl839x_set_egress_queue(int port, int queue);
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