mirror/openwrt
1
0
Fork 1
mirror of https://git.openwrt.org/openwrt/openwrt.git synced 2026-01-27 21:27:18 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 6

realtek: pcs: rtl931x: add sequence for LC PLL
Some checks are pending
Build Kernel / Build all affected Kernels (push) Waiting to run
Details

Browse source 
The RTL931X CMU code was only capable of setting up ring PLL. This is
fine so far as most modes use this PLL type. Other modes are not handled
by the code, neither here nor in the SDK. Though, the SDK has the needed
sequence to setup the LC PLL. Using LC PLL seems to be handled somewhere
else.

Include the small sequence from the SDK to have it, though not used yet.
This could be helpful for further development which goes beyond the SDK.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21707
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Jonas Jelonek 2026-01-25 19:52:37 +00:00 • committed by Robert Marko
parent 638ccb6760
commit 180f53d285
1 changed files with 15 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
View file

@ -2985,11 +2985,9 @@ static int rtpcs_931x_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo
return -EINVAL; return -EINVAL;
} }
if (pll_type == RTPCS_SDS_PLL_RING) { cmu_page = rtpcs_931x_sds_cmu_page_get(hw_mode);
cmu_page = rtpcs_931x_sds_cmu_page_get(hw_mode); if (cmu_page < 0)
if (cmu_page < 0) return -EINVAL;
return -EINVAL;
}
if (sds == even_sds) { if (sds == even_sds) {
force_lc_mode_bit = 4; force_lc_mode_bit = 4;
@ -3015,6 +3013,18 @@ static int rtpcs_931x_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mo
force_lc_mode_val_bit, 0x0); force_lc_mode_val_bit, 0x0);
rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 12, 12, 0x1); rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 12, 12, 0x1);
rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 15, 13, force_pll_spd ? 0x1 : 0x0); rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 15, 13, force_pll_spd ? 0x1 : 0x0);
} else if (pll_type == RTPCS_SDS_PLL_LC) {
rtpcs_sds_write_bits(sds, cmu_page, 0x7, 15, 15, 0x1);
if (chiptype)
rtpcs_sds_write_bits(sds, cmu_page, 0xd, 14, 14, 1);
rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 1, 0, 0x3);
rtpcs_sds_write_bits(even_sds, 0x20, 0x12, force_lc_mode_bit,
force_lc_mode_bit, 0x1);
rtpcs_sds_write_bits(even_sds, 0x20, 0x12, force_lc_mode_val_bit,
force_lc_mode_val_bit, 0x1);
rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 8, 8, 0x1);
rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 11, 9, force_pll_spd ? 0x1 : 0x0);
} }
return 0; return 0;