update for newer Gowin IDE

This commit is contained in:
Steve Markgraf 2025-11-29 01:12:07 +01:00
parent a9bc725209
commit c03f45e226
9 changed files with 147 additions and 39 deletions

1
.gitignore vendored Normal file
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impl/*

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@ -5,7 +5,13 @@ This repository contains the FPGA implementation and example designs for the Tan
The example design generates a 16 bit counter, that then can be verified on the host. With a small modification to the clk_data process in the top-file of your respective FPGA board you can stream your own payload data. The example design generates a 16 bit counter, that then can be verified on the host. With a small modification to the clk_data process in the top-file of your respective FPGA board you can stream your own payload data.
## Building the desgin ## Building the desgin
Currently, the bitfiles must be generated with the GOWIN IDE (V1.9.9 Beta-4 Education). See [here](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-Doc/install-the-ide.html) for more information on how to set up the IDE. Currently, the bitfiles must be generated with the GOWIN IDE (V1.9.11.03 Education). See [here](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-Doc/install-the-ide.html) for more information on how to set up the IDE.
For launching on Arch Linux:
rm ./IDE/lib/libfreetype.so.6
LD_LIBRARY_PATH=./IDE/lib/ ./IDE/bin/gw_ide
In the future, it might be possible to use the Open Source toolchain ([Yosys](https://github.com/YosysHQ/yosys) + [nextpnr-himbaechel](https://github.com/YosysHQ/nextpnr) + [apicula](https://github.com/YosysHQ/apicula)). This is currently blocked by the lack of the CLKDIV primitive In the future, it might be possible to use the Open Source toolchain ([Yosys](https://github.com/YosysHQ/yosys) + [nextpnr-himbaechel](https://github.com/YosysHQ/nextpnr) + [apicula](https://github.com/YosysHQ/apicula)). This is currently blocked by the lack of the CLKDIV primitive
in the Open Source tools. in the Open Source tools.

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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="0"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/hsdaoh_nano20k_test.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/hsdaoh_nano20k_test.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/hsdaoh_nano20k_test.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/hsdaoh_nano20k_test.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/hsdaoh_nano20k_test.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/hsdaoh_nano20k_test.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/hsdaoh_nano20k_test.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/hsdaoh_nano20k_test.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/hsdaoh_nano20k_test_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/hsdaoh_nano20k_test_syn_rsc.xml"/>
</ResultFileList>
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<FpUi></FpUi>
</UserConfig>

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@ -1,21 +1,8 @@
//IO_LOC "led[5]" 15;
//IO_PORT "led[5]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8;
//IO_LOC "led[4]" 13;
//IO_PORT "led[4]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8;
//IO_LOC "led[3]" 10;
//IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8;
//IO_LOC "led[2]" 16;
//IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8;
//IO_LOC "led[1]" 14;
//IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8;
//IO_LOC "led[0]" 11;
//IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8;
IO_LOC "sys_resetn" 88; IO_LOC "sys_resetn" 88;
IO_PORT "sys_resetn" PULL_MODE=UP; IO_PORT "sys_resetn" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_LOC "sys_clk" 4; IO_LOC "sys_clk" 4;
IO_PORT "sys_clk" IO_TYPE=LVCMOS33;
//IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_PORT "sys_clk" PULL_MODE=UP; IO_PORT "sys_clk" PULL_MODE=UP;
IO_LOC "tmds_d_p[0]" 35,36; IO_LOC "tmds_d_p[0]" 35,36;
IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8; IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8;
@ -25,23 +12,3 @@ IO_LOC "tmds_d_p[2]" 39,40;
IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=8; IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=8;
IO_LOC "tmds_clk_p" 33,34; IO_LOC "tmds_clk_p" 33,34;
IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=8; IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=8;
// 20k example:
//IO_LOC "O_tmds_clk_p" 33,34;
//IO_PORT "O_tmds_clk_p" PULL_MODE=NONE DRIVE=8;
//IO_LOC "O_tmds_data_p[0]" 35,36;
//IO_PORT "O_tmds_data_p[0]" PULL_MODE=NONE DRIVE=8;
//IO_LOC "O_tmds_data_p[1]" 37,38;
//IO_PORT "O_tmds_data_p[1]" PULL_MODE=NONE DRIVE=8;
//IO_LOC "O_tmds_data_p[2]" 39,40;
//IO_PORT "O_tmds_data_p[2]" PULL_MODE=NONE DRIVE=8;
//IO_LOC "I_clk" 4;
//IO_PORT "I_clk" PULL_MODE=UP;

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@ -0,0 +1,27 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="0"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/hsdaoh_nano4k_test.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/hsdaoh_nano4k_test.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/hsdaoh_nano4k_test.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/hsdaoh_nano4k_test.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/hsdaoh_nano4k_test.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/hsdaoh_nano4k_test.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/hsdaoh_nano4k_test.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/hsdaoh_nano4k_test.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/hsdaoh_nano4k_test_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/hsdaoh_nano4k_test_syn_rsc.xml"/>
</ResultFileList>
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<FpUi></FpUi>
</UserConfig>

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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="0"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/hsdaoh_nano9k_test.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/hsdaoh_nano9k_test.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/hsdaoh_nano9k_test.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/hsdaoh_nano9k_test.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/hsdaoh_nano9k_test.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/hsdaoh_nano9k_test.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/hsdaoh_nano9k_test.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/hsdaoh_nano9k_test.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/hsdaoh_nano9k_test_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/hsdaoh_nano9k_test_syn_rsc.xml"/>
</ResultFileList>
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<FpUi></FpUi>
</UserConfig>

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@ -0,0 +1,27 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="4"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="0"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/hsdaoh_primer20k_test.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/hsdaoh_primer20k_test.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/hsdaoh_primer20k_test.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/hsdaoh_primer20k_test.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/hsdaoh_primer20k_test.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/hsdaoh_primer20k_test.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/hsdaoh_primer20k_test.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/hsdaoh_primer20k_test.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/hsdaoh_primer20k_test_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/hsdaoh_primer20k_test_syn_rsc.xml"/>
</ResultFileList>
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<FpUi></FpUi>
</UserConfig>

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@ -1,8 +1,7 @@
IO_LOC "sys_resetn" T10; IO_LOC "sys_resetn" T10;
IO_PORT "sys_resetn" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_PORT "sys_resetn" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_LOC "sys_clk" H11; IO_LOC "sys_clk" H11;
//IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_PORT "sys_clk" PULL_MODE=UP;
IO_LOC "tmds_d_p[0]" H14,H16; IO_LOC "tmds_d_p[0]" H14,H16;
IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8; IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8;
IO_LOC "tmds_d_p[1]" J15,K16; IO_LOC "tmds_d_p[1]" J15,K16;

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@ -0,0 +1,27 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="0"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/hsdaoh_primer25k_test.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/hsdaoh_primer25k_test.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/hsdaoh_primer25k_test.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/hsdaoh_primer25k_test.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/hsdaoh_primer25k_test.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/hsdaoh_primer25k_test.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/hsdaoh_primer25k_test.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/hsdaoh_primer25k_test.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/hsdaoh_primer25k_test_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/hsdaoh_primer25k_test_syn_rsc.xml"/>
</ResultFileList>
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<FpUi></FpUi>
</UserConfig>