From c03f45e226f793da80db19b5fb6c4c03718088bf Mon Sep 17 00:00:00 2001 From: Steve Markgraf Date: Sat, 29 Nov 2025 01:12:07 +0100 Subject: [PATCH] update for newer Gowin IDE --- .gitignore | 1 + README.md | 8 +++- hsdaoh_nano20k_test.gprj.user | 27 +++++++++++++ hsdaoh_nano20k_test/hsdaoh_nano20k_test.cst | 39 ++----------------- hsdaoh_nano4k_test.gprj.user | 27 +++++++++++++ hsdaoh_nano9k_test.gprj.user | 27 +++++++++++++ hsdaoh_primer20k_test.gprj.user | 27 +++++++++++++ .../hsdaoh_primer20k_test.cst | 3 +- hsdaoh_primer25k_test.gprj.user | 27 +++++++++++++ 9 files changed, 147 insertions(+), 39 deletions(-) create mode 100644 .gitignore create mode 100644 hsdaoh_nano20k_test.gprj.user create mode 100644 hsdaoh_nano4k_test.gprj.user create mode 100644 hsdaoh_nano9k_test.gprj.user create mode 100644 hsdaoh_primer20k_test.gprj.user create mode 100644 hsdaoh_primer25k_test.gprj.user diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..7d2cc32 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +impl/* diff --git a/README.md b/README.md index 1ddb954..513bcdc 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,13 @@ This repository contains the FPGA implementation and example designs for the Tan The example design generates a 16 bit counter, that then can be verified on the host. With a small modification to the clk_data process in the top-file of your respective FPGA board you can stream your own payload data. ## Building the desgin -Currently, the bitfiles must be generated with the GOWIN IDE (V1.9.9 Beta-4 Education). See [here](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-Doc/install-the-ide.html) for more information on how to set up the IDE. +Currently, the bitfiles must be generated with the GOWIN IDE (V1.9.11.03 Education). See [here](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-Doc/install-the-ide.html) for more information on how to set up the IDE. + +For launching on Arch Linux: + + rm ./IDE/lib/libfreetype.so.6 + LD_LIBRARY_PATH=./IDE/lib/ ./IDE/bin/gw_ide + In the future, it might be possible to use the Open Source toolchain ([Yosys](https://github.com/YosysHQ/yosys) + [nextpnr-himbaechel](https://github.com/YosysHQ/nextpnr) + [apicula](https://github.com/YosysHQ/apicula)). This is currently blocked by the lack of the CLKDIV primitive in the Open Source tools. diff --git a/hsdaoh_nano20k_test.gprj.user b/hsdaoh_nano20k_test.gprj.user new file mode 100644 index 0000000..b5b6395 --- /dev/null +++ b/hsdaoh_nano20k_test.gprj.user @@ -0,0 +1,27 @@ + + + + 1.0 + + + + + + + + + + + + + + + + + + + + + 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+ + diff --git a/hsdaoh_nano20k_test/hsdaoh_nano20k_test.cst b/hsdaoh_nano20k_test/hsdaoh_nano20k_test.cst index c23997b..bdfe002 100644 --- a/hsdaoh_nano20k_test/hsdaoh_nano20k_test.cst +++ b/hsdaoh_nano20k_test/hsdaoh_nano20k_test.cst @@ -1,21 +1,8 @@ -//IO_LOC "led[5]" 15; -//IO_PORT "led[5]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; -//IO_LOC "led[4]" 13; -//IO_PORT "led[4]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; -//IO_LOC "led[3]" 10; -//IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; -//IO_LOC "led[2]" 16; -//IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; -//IO_LOC "led[1]" 14; -//IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; -//IO_LOC "led[0]" 11; -//IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8; - IO_LOC "sys_resetn" 88; -IO_PORT "sys_resetn" PULL_MODE=UP; +IO_PORT "sys_resetn" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_LOC "sys_clk" 4; +IO_PORT "sys_clk" IO_TYPE=LVCMOS33; -//IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_PORT "sys_clk" PULL_MODE=UP; IO_LOC "tmds_d_p[0]" 35,36; IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8; @@ -24,24 +11,4 @@ IO_PORT "tmds_d_p[1]" PULL_MODE=NONE DRIVE=8; IO_LOC "tmds_d_p[2]" 39,40; IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=8; IO_LOC "tmds_clk_p" 33,34; -IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=8; - - - - - - - - - -// 20k example: -//IO_LOC "O_tmds_clk_p" 33,34; -//IO_PORT "O_tmds_clk_p" PULL_MODE=NONE DRIVE=8; -//IO_LOC "O_tmds_data_p[0]" 35,36; -//IO_PORT "O_tmds_data_p[0]" PULL_MODE=NONE DRIVE=8; -//IO_LOC "O_tmds_data_p[1]" 37,38; -//IO_PORT "O_tmds_data_p[1]" PULL_MODE=NONE DRIVE=8; -//IO_LOC "O_tmds_data_p[2]" 39,40; -//IO_PORT "O_tmds_data_p[2]" PULL_MODE=NONE DRIVE=8; -//IO_LOC "I_clk" 4; -//IO_PORT "I_clk" PULL_MODE=UP; \ No newline at end of file +IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=8; \ No newline at end of file diff --git a/hsdaoh_nano4k_test.gprj.user b/hsdaoh_nano4k_test.gprj.user new file mode 100644 index 0000000..fda18f4 --- /dev/null +++ b/hsdaoh_nano4k_test.gprj.user @@ -0,0 +1,27 @@ + + + + 1.0 + + + + + + + + + + + + + + + + + + + + + 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+ + diff --git a/hsdaoh_nano9k_test.gprj.user b/hsdaoh_nano9k_test.gprj.user new file mode 100644 index 0000000..fef2056 --- /dev/null +++ b/hsdaoh_nano9k_test.gprj.user @@ -0,0 +1,27 @@ + + + + 1.0 + + + + + + + + + + + + + + + + + + + + + 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+ + diff --git a/hsdaoh_primer20k_test.gprj.user b/hsdaoh_primer20k_test.gprj.user new file mode 100644 index 0000000..6e46c9e --- /dev/null +++ b/hsdaoh_primer20k_test.gprj.user @@ -0,0 +1,27 @@ + + + + 1.0 + + + + + + + + + + + + + + + + + + + + + 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+ + diff --git a/hsdaoh_primer20k_test/hsdaoh_primer20k_test.cst b/hsdaoh_primer20k_test/hsdaoh_primer20k_test.cst index 2369876..e1eedf5 100644 --- a/hsdaoh_primer20k_test/hsdaoh_primer20k_test.cst +++ b/hsdaoh_primer20k_test/hsdaoh_primer20k_test.cst @@ -1,8 +1,7 @@ IO_LOC "sys_resetn" T10; IO_PORT "sys_resetn" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_LOC "sys_clk" H11; -//IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; -IO_PORT "sys_clk" PULL_MODE=UP; +IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_LOC "tmds_d_p[0]" H14,H16; IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8; IO_LOC "tmds_d_p[1]" J15,K16; diff --git a/hsdaoh_primer25k_test.gprj.user b/hsdaoh_primer25k_test.gprj.user new file mode 100644 index 0000000..efbe35c --- /dev/null +++ b/hsdaoh_primer25k_test.gprj.user @@ -0,0 +1,27 @@ + + + + 1.0 + + + + + + + + + + + + + + + + + + + + + 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+ +