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WIP: first test with yosys/nextpnr/apicula

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This commit is contained in:
Steve Markgraf 2024-07-12 21:13:09 +02:00
parent ff425280b1
commit 2bfe1c635a
3 changed files with 60 additions and 2 deletions
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36
Makefile Normal file
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@ -0,0 +1,36 @@
YOSYS ?= yosys
NEXTPNR ?= nextpnr-himbaechel
.DEFAULT_GOAL := all
all: \
hsdaoh-tangnano20k.fs
unpacked:\
hsdaoh-tangnano20k-unpacked.v \
clean:
rm -f *.json *.fs *-unpacked.v
.PHONY: unpacked clean
# ============================================================
# Tangnano20k
%-tangnano20k.fs: %-tangnano20k.json
gowin_pack -d GW2A-18C -o $@ $<
%-tangnano20k.json: %-tangnano20k-synth.json tangnano20k.cst
$(NEXTPNR) --json $< --write $@ --device GW2AR-LV18QN88C8/I7 --vopt family=GW2A-18C --vopt cst=tangnano20k.cst
%-tangnano20k-synth.json: %.v
$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
hsdaoh-tangnano20k-synth.json: hsdaoh_nano20k_test/top.v common/hsdaoh/hsdaoh_core.v common/hdmi/auxiliary_video_information_info_frame.v common/hdmi/hdmi.v common/hdmi/packet_assembler.v common/hdmi/packet_picker.v common/hdmi/serializer.v common/hdmi/tmds_channel.v common/async_fifo/async_fifo.v common/async_fifo/fifomem.v common/async_fifo/rptr_empty.v common/async_fifo/sync_r2w.v common/async_fifo/sync_w2r.v common/async_fifo/wptr_full.v
$(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@"
# ============================================================
# Upack
%-tangnano20k-unpacked.v: %-tangnano20k.fs
gowin_unpack -d GW2A-18C -o $@ $^

2
hsdaoh_nano20k_test/top.v
View file

@ -6,7 +6,6 @@
module top ( module top (
sys_clk, sys_clk,
sys_resetn, sys_resetn,
enable,
tmds_clk_n, tmds_clk_n,
tmds_clk_p, tmds_clk_p,
tmds_d_n, tmds_d_n,
@ -14,7 +13,6 @@ module top (
); );
input sys_clk; input sys_clk;
input sys_resetn; input sys_resetn;
input wire enable;
output wire tmds_clk_n; output wire tmds_clk_n;
output wire tmds_clk_p; output wire tmds_clk_p;
output wire [2:0] tmds_d_n; output wire [2:0] tmds_d_n;

24
tangnano20k.cst Normal file
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@ -0,0 +1,24 @@
IO_LOC "sys_resetn" 88;
IO_PORT "sys_resetn" PULL_MODE=UP;
IO_LOC "sys_clk" 4;
//IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP;
IO_PORT "sys_clk" PULL_MODE=UP;
IO_LOC "tmds_d_p[0]" 35;
IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8;
IO_LOC "tmds_d_p[1]" 37;
IO_PORT "tmds_d_p[1]" PULL_MODE=NONE DRIVE=8;
IO_LOC "tmds_d_p[2]" 39;
IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=8;
IO_LOC "tmds_clk_p" 33;
IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=8;
IO_LOC "tmds_d_n[0]" 36;
IO_PORT "tmds_d_n[0]" DRIVE=8;
IO_LOC "tmds_d_n[1]" 38;
IO_PORT "tmds_d_n[1]" DRIVE=8;
IO_LOC "tmds_d_n[2]" 40;
IO_PORT "tmds_d_n[2]" DRIVE=8;
IO_LOC "tmds_clk_n" 34;
IO_PORT "tmds_clk_n" DRIVE=8;