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https://github.com/steve-m/hsdaoh-fpga.git
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36 lines
1.2 KiB
Makefile
36 lines
1.2 KiB
Makefile
YOSYS ?= yosys
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NEXTPNR ?= nextpnr-himbaechel
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.DEFAULT_GOAL := all
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all: \
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hsdaoh-tangnano20k.fs
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unpacked:\
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hsdaoh-tangnano20k-unpacked.v \
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clean:
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rm -f *.json *.fs *-unpacked.v
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.PHONY: unpacked clean
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# ============================================================
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# Tangnano20k
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%-tangnano20k.fs: %-tangnano20k.json
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gowin_pack -d GW2A-18C -o $@ $<
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%-tangnano20k.json: %-tangnano20k-synth.json tangnano20k.cst
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$(NEXTPNR) --json $< --write $@ --device GW2AR-LV18QN88C8/I7 --vopt family=GW2A-18C --vopt cst=tangnano20k.cst
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%-tangnano20k-synth.json: %.v
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$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
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hsdaoh-tangnano20k-synth.json: hsdaoh_nano20k_test/top.v common/hsdaoh/hsdaoh_core.v common/hdmi/auxiliary_video_information_info_frame.v common/hdmi/hdmi.v common/hdmi/packet_assembler.v common/hdmi/packet_picker.v common/hdmi/serializer.v common/hdmi/tmds_channel.v common/async_fifo/async_fifo.v common/async_fifo/fifomem.v common/async_fifo/rptr_empty.v common/async_fifo/sync_r2w.v common/async_fifo/sync_w2r.v common/async_fifo/wptr_full.v
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$(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@"
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# ============================================================
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# Upack
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%-tangnano20k-unpacked.v: %-tangnano20k.fs
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gowin_unpack -d GW2A-18C -o $@ $^
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