1
0
Fork 0
forked from mirror/openwrt
openwrt/target/linux/ramips/dts/mt7621_arcadyan_we410443.dts
Shiji Yang 98b160acd2 ramips: fix wrong CRLF line-ending
Use Unix LF style instead of Windows CRLF style.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19963
Signed-off-by: Robert Marko <robimarko@gmail.com>
2025-09-07 11:36:55 +02:00

197 lines
3.3 KiB
Text
Executable file

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7621.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Arcadyan WE410443";
compatible = "arcadyan,we410443", "mediatek,mt7621-soc";
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_red;
led-running = &led_status_green;
led-upgrade = &led_status_blue;
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_status_blue: blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio 41 GPIO_ACTIVE_HIGH>;
};
led_status_green: green {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
};
led_status_red: red {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "all";
reg = <0x0 0x2000000>;
read-only;
};
partition@1 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom_factory_0: eeprom@0 {
reg = <0x0 0x4da8>;
};
eeprom_factory_8000: eeprom@8000 {
reg = <0x8000 0x4da8>;
};
};
};
partition@50000 {
compatible = "fixed-partitions";
label = "firmware";
reg = <0x50000 0x1f60000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x440000>;
};
partition@400000 {
label = "rootfs";
reg = <0x440000 0x1b20000>;
};
};
partition@1fb0000 {
label = "glbcfg";
reg = <0x1fb0000 0x10000>;
read-only;
};
partition@1fc0000 {
label = "config";
reg = <0x1fc0000 0x10000>;
read-only;
};
partition@1fd0000 {
label = "glbcfg2";
reg = <0x1fd0000 0x10000>;
read-only;
};
partition@1fe0000 {
label = "config2";
reg = <0x1fe0000 0x10000>;
read-only;
};
};
};
};
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
ieee80211-freq-limit = <2400000 2500000>;
};
};
&pcie1 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_8000>;
nvmem-cell-names = "eeprom";
ieee80211-freq-limit = <5000000 6000000>;
};
};
&state_default {
gpio {
groups = "i2c", "wdt", "sdhci";
function = "gpio";
};
};
&switch0 {
ports {
port@0 {
status = "okay";
label = "lan";
};
};
};
&xhci {
status = "disabled";
};