This commit adds support for RTL9607C/RTL8198D clocks to the existing
clk-rtl83xx driver. Setting clock rates is not supported due to
lack of knowledge on this topic at the moment. Clocks for CPU1, SRAM
and SPI can also be calculated but not included in this commit.
Since the registers, calculations are widely different to RTL83XX it
was decide to have different clk_ops for RTL960X.
The code was partly based on naseef's work with some changes to
integrate it into the clk-rtl83xx driver.
Tested-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/22080
Signed-off-by: Robert Marko <robimarko@gmail.com>
Currently, devices having two cpu ports to the switch managed by swconfig,
especally those with qca955x, line tplink archer c7 v2 and linksys ea4500 v3,
use vlan on different cpu port to separate networks by default. (e.g. eth1.1
for lan, eth0.2 for wan)
However, untagging to these vlans cpu ports, and limiting vlans in the switch
on these devices could effectively offload the expense to process vlan tag from
cpu to the switch, and increase the throughput of lan <-> wan ipoe routing.
Tested on my tplink tl-wdr4900 v2, where ucidef_add_switch "switch0"
"0u@eth1" "2:lan" "3:lan" "4:lan" "5:lan" "6u@eth0" "1:wan" finally generates
on /etc/config/network:
config device
option name 'br-lan'
option type 'bridge'
list ports 'eth1'
config interface 'lan'
option device 'br-lan'
option proto 'static'
list ipaddr '192.168.1.1/24'
option ip6assign '60'
config interface 'wan'
option device 'eth0'
option proto 'dhcp'
config interface 'wan6'
option device 'eth0'
option proto 'dhcpv6'
config switch
option name 'switch0'
option reset '1'
option enable_vlan '1'
config switch_vlan
option device 'switch0'
option vlan '1'
option ports '2 3 4 5 0'
config switch_vlan
option device 'switch0'
option vlan '2'
option ports '1 6'
and the throughput of lan <-> wan ipoe routing with software flow offload
increases from around
[850 Mbps](https://openwrt.org/toh/tp-link/archer-c5-c7-wdr7500#nat_performance)
to 900 Mbps.
Signed-off-by: Edward Chow <equu@openmail.cc>
Link: https://github.com/openwrt/openwrt/pull/19444
Signed-off-by: Robert Marko <robimarko@gmail.com>
These devices use the binding + eeprom-swap. Turns out the reason swap
is needed is because the binding wrongly swaps the data on big endian
hosts. NVMEM doesn't do this and thus just works.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22207
Signed-off-by: Robert Marko <robimarko@gmail.com>
A size of 600 is incomplete in that calibration data is not included,
resulting in low TX power.
Fixes: 64dae105 ("ramips: mt76x8: add support for Yuncore CPE200")
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22459
Signed-off-by: Robert Marko <robimarko@gmail.com>
The dtsi used handles a bunch of non-DBDC platforms where the
assignments are correct. The 3040-a1 is different as there are 3 instead
of 2 wifi interfaces and WAN needs to be incremented by 1.
Remove userspace wifi assignmwent which was needed before per band nvmem
was supported.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21977
Signed-off-by: Robert Marko <robimarko@gmail.com>
While rebasing, a typo was made where the ';;' terminator was omitted in
the 02_network script. Add it to restore script functionality.
Fixes: e210d994fa ("airoha: an7581: add Nokia Valyrian support")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
- Update network port names based on the shell
- Fix boot log errors:
OF: /soc/pcie@11280000/pcie@0,0: Missing device_type
- Match vendor firmware Ethernet and wireless MAC addresses
LAN MAC 50:xx:xx:xx:xx:60
WAN MAC 50:xx:xx:xx:xx:61
2G MAC 50:xx:xx:xx:xx:63
5G MAC 50:xx:xx:xx:xx:65
Fixes: 7d79346581 ("mediatek: filogic: add support for Tenda BE12 Pro")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/22060
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Add support for Nokia Valyrian based on Airoha AN7581 SoC.
Device specification
--------------------
SoC Type: Airoha AN7581
RAM: 2x DDR4 Nanya NT5AD256M16E4-JR (1GB)
Flash: eMMC Macronix MX52LM08A11XVW (1GB)
Ethernet: 3x gigabit via AN7581, 1x 10g via AS21x1x, 1x SFP cage
Wi-Fi: MT7996 - BE19000
LEDs: 11 LED via 2x 74HC595 shift register
Button: Reset, WPS, WiFi
USB ports: 1x 2.0
Miscellaneous: 1x Power Monitor via RTQ6059, 2x FXS port
Device is unfused and is originally flashed with Airoha SDK bootloader
that require signed images.
Bootloader is username/password protected and use the leaked auth combo
that can be found online.
From the bootloadet instruction on how to flash custom bootloader are:
1. mmc erase 0 0x800
2. tftpboot 192.168.1.10:airoha/an7581/openwrt-airoha-an7581-nokia_valyrian-preloader.bin
3. mmc write $loadaddr 0x4 0xfc
4. tftpboot 192.168.1.10:airoha/an7581/openwrt-airoha-an7581-nokia_valyrian-bl31-uboot.fip
5. mmc write $loadaddr 0x100 0x700
It's also possible to use the Emergency Recovery procedure:
From powered OFF device:
1. Keep the reset button pressed (middle button)
2. Power on the device
3. Notice the "Press x" prompt
4. Press x
5. Notice the "C" char waiting for XMODEM load
6. Load the preloader binary with XMODEM protocol
7. Notice the "Press x to load BL31 + U-Boot FIP"
8. Press x
9. Notice the "C" char waiting for XMODEM load
10. Load the fip binary with XMODEM protocol
11. You are now in U-Boot loaded from serial
12. Follow normal procedure to flash bootloader
Due to BOOTROM limitation. the device can't have a standard GPT table
implementation. Because of this fixed-partitions are used to handle this.
U-Boot still doesn't have support for this (it's planned) and currently to flash
and load and image it's needed to write and read from static address in eMMC.
The GPT partition table follow Prpl guidelines with dual partition table with
kernel and rootfs split.
The address for kernel is 0xb00000 and the address for rootfs is 0x1b00000.
Link: https://github.com/openwrt/openwrt/pull/21761
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Set nand flash for KN-1910
Sysupgrade or any other method i tried (asu, owut) not working without it. Tested with a local build.
Signed-off-by: Esat Yiğithan GÖKTOPRAK <eygoktoprak@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22311
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The bootcount init script is missing the executable bit (644 instead of 755),
causing the script to not be executable:
/etc/preinit: line 44: /etc/init.d/bootcount: Permission denied
Fixes: c3b8108a2b ("ramips: Add support for Xiaomi MiWiFi 3A")
Signed-off-by: Oliver Sedlbauer <os@dev.tdt.de>
Link: https://github.com/openwrt/openwrt/pull/22446
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MIPS code assigns the clock node based on the device tree node name.
This name was renamed with kernel 6.12.58 and v6.6.117. Adapt our out of
tree device tree files to this rename to fix loading the STP GPIO
driver.
Without this fix the driver fails like this:
```
[ 0.320000] gpio-stp-xway 1e100bb0.stp: Failed to get clock
[ 0.330000] gpio-stp-xway 1e100bb0.stp: probe with driver gpio-stp-xway failed with error -2
```
Link: https://git.kernel.org/linus/b0d04fe6a633ada2c7bc1b5ddd011cbd85961868
Fixes: https://github.com/openwrt/openwrt/issues/21697
Co-Authored-By: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22444
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Certain targets for an7581 and an7583 referred to kmod-pwm-airoha;
however in the target modules makefile the module is referred to
as kmod-pwm-an7581, causing buildbot to fail.
Change the name of kmod-pwm-an7581 to kmod-pwm-airoha to resolve this.
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/22445
Signed-off-by: Robert Marko <robimarko@gmail.com>
W1700K fan script is missing the #!/bin/sh /etc/rc.common shebang and
requires execution bits set. Also, set the fallback to hwmon 3 instead
of 5, since the new RTL PHY driver was not merged.
Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22391
Signed-off-by: Robert Marko <robimarko@gmail.com>
Note that for working G.hn support some packages need to be extracted from the Devolo firmware.
Signed-off-by: Julius Schwartzenberg <julius.schwartzenberg@eclipso.eu>
Link: https://github.com/openwrt/openwrt/pull/22123
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Developers no longer maintain this driver. And it has been replaced
by the new upstream implementation. It's time to say goodbye.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22214
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is the generic PWM framework driver for Mediatek SoC. Now
this module is ready for MT7628.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22214
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The upstream MediaTek PWM driver requires these clock sources to
work properly.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22214
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
When running `make kernel_menuconfig`, CPU_BIG_ENDIAN is selected by
default, resulting in a non-bootable image. Add CPU_LITTLE_ENDIAN to
avoid that.
Signed-off-by: Qingfang Deng <dqfext@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22282
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The device dts files were moved to the dedicated directory in commit
a66e30631c ("qualcommax: move Device DTS to dedicated DTS directory"),
which resulted in a merge conflict.
Fixes: d755c49f7a ("qualcommax: ipq60xx: rename TP-Link EAP623-Outdoor HD v1 compatible")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22433
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit adds support for RTL9607C / RTL8198D thermal controller.
Based on the Realtek SDK code.
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/22081
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL8226 PHYs in Zyxel XGS1010-10 and XGS1210-10 rev A1 have swapped
MDI lanes. Specify this in the device tree, so the driver can configure
it. With this change, the PHYs no longer require initialization by the
bootloader.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21261
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The PHY supports swapping the MDI pairs (ABCD->DCBA) to simplify board
layout. On devices making use of this, it needs to be configured in the
driver, otherwise the PHY won't work properly.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21261
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The dsa irq handler works always in the same way for all SoCs.
- Read register ISR_PORT_LINK_STS_CHG to determine the ports that
triggered the irq.
- Write the read value back to the register to confirm the irq
- Read link status via MAC_LINK_STS
- Trigger dsa_port_phylink_mac_change() for each changed port
Currently each SoC has its own implementation. Drop that in
favour of a generic implementation that makes use of the existing
bit register read/write helpers.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22273
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This register will be needed to provide a generic irq handler. Add
it to the configuration structure of the driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22273
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some 10G optics showed random "module transmit fault indicated" due to I2C
read errors on ONTi ONT-S508CL-8S/XikeStor SKS8300-8X switches. The same
modules work with the original firmware and on other Linux based devices.
There seems to be some differences in how we talk to those modules using
I2C in OpenWRT. To fix this this patch adds support for 50kHz I2C speed on
SFPs and enables that for XikeStor/Onti devices. Since SFPs only transmit
very few bytes this should not have any real downsides.
This patch configures I2C to use 50kHz clock in the DTS for the affected
devices. For it to work it requires a change in the RTL9300 I2C driver.
This can be safely merged without the kernel change (but will not work
in that case as it will fall back to 100kHz).
Signed-off-by: Jan Kantert <jan-openwrt@kantert.net>
Link: https://github.com/openwrt/openwrt/pull/22210
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
No functional changes intended.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/22350
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The main difference between EAP610, 623, and 625 is the device name,
support string, and the BDF package. Move the others to a common
Device/tplink_eap6xx-common in order to highlight the common aspects.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18804
Signed-off-by: Robert Marko <robimarko@gmail.com>
The EAP625 and EAP623 are extremely similar. The only difference in
the vendor's device tree is that EAP625 also enables USB and UART2.
Use the eap6xx dtsi instead of writing out a full devicetree.
The EAP623 uses the same RTL8211F as the 625 and 610. Since this is
a gigabit PHY, it is okay to change the ess mac mode from SGMII_PLUS
to SGMII. This is now consistent across all three devices.
Move the 'realtek,clkout-disable' and 'realtek,aldps-enable' PHY
properties to the common dtsi, as they work well on all three devices.
Reflect the remaining differences in the eap625 dts.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18804
Signed-off-by: Robert Marko <robimarko@gmail.com>
As I was looking at the differences between EAP610, 623, and 625
Outdoor, I realized that the quick-start guide of all of the devices
mentions a yellow and green LED. Thus rename the "amber" led to
"yellow", and adjust its color ID accordingly.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18804
Signed-off-by: Robert Marko <robimarko@gmail.com>
Originally, the .compatible string for EAP623-Outdoor HD tried to
shorten the "-outdoor" to "od". However, this naming was inconsistent
with the existing "eap610-outdoor". As "od" is not a common shorthand,
spell out the complete word: "eap623-outdoor-hd-v1".
Fixes: 5dbf93c8c5 ("ipq60xx: add support for TP-Link EAP623-Outdoor HD v1")
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18804
Signed-off-by: Robert Marko <robimarko@gmail.com>
CI is currently failing due to these four patches.
Automatically refreshed with `make target/linux/refresh`.
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/22399
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Since the u-boot ethaddr variable is quoted, we cannot use it.
Use mac-base instead to specify in dts.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/14182
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/14182
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/14182
Signed-off-by: Robert Marko <robimarko@gmail.com>
Removes deprecated userspace handling.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/14182
Signed-off-by: Robert Marko <robimarko@gmail.com>
- Fix RTL8261N 10GbE PHY `reset-deassert-us` from 100ms to 221ms to meet datasheet minimum SMI-ready timing (t7 >= 150ms), fixing intermittent boot stalls caused by MDIO bus instability
- Add missing WLAN toggle button (GPIO 34) present in stock firmware but absent from OpenWrt DTS
- Fix memory size from 1 GB to the actual 512 MB
Fix 1: The RTL8261N 10GbE PHY's `reset-deassert-us` was set to 100ms (100000us), but the **RTL8261N datasheet (Table 108, parameter t7)** specifies a minimum **SMI-ready time of 150ms** after nRESET release before the MDIO (SMI) bus can be used.
With only 100ms, the kernel attempts MDIO bus access before the RTL8261N's SMI interface is stable. Since the RTL8261N (mdio-bus:00) and the internal MT7988 2.5GbE PHY (mdio-bus:0f) share the same MDIO bus, a not-yet-ready RTL8261N disrupts all MDIO traffic, causing the 2.5GbE PHY firmware loading (`mt798x_2p5ge_phy_config_init`) to stall.
Observed symptoms on warm reboot:
- Sometimes `mt798x_2p5ge_phy_config_init` hangs for 5+ minutes or indefinitely
- RCU CPU stalls (`rcu: INFO: rcu_sched detected stalls on CPUs`)
- mt7996e WiFi chip message timeouts cascading to `chip full reset failed`
- System appears hung with only power LED blinking slowly
UART serial log evidence (warm reboot with 100ms):
```
[ 73.041756] rcu: INFO: rcu_sched self-detected stall on CPU
[ 73.048341] rcu: 2-....: (8 ticks this GP)
[ 73.061641] pc : mt798x_2p5ge_phy_config_init+0x258/0xbb0
[ 73.061653] lr : mt798x_2p5ge_phy_config_init+0x238/0xbb0
...
[ 334.771280] MediaTek MT7988 2.5GbE PHY mdio-bus:0f: Firmware date code: 2024/10/30
```
The 2.5GbE PHY firmware loading, which normally takes ~3 seconds, took **325 seconds** due to MDIO bus instability. In the worst case, the system never recovers.
GPL DTS uses 221ms (`reset-deassert-us = <221000>`), providing 71ms of margin above the 150ms datasheet minimum. All MediaTek MT7988 reference board DTS files in the GPL use this same 221ms value.
Fix 2: Missing WLAN button (GPIO 34)
The BE450 has a physical WLAN toggle button on GPIO 34, defined in the stock TP-Link GPL DTS but missing from the OpenWrt DTS. Without this definition, the button is non-functional under OpenWrt.
The pin name for GPIO 34 in the MT7988 pinctrl is `SPI2_MISO`, confirmed by the kernel pinctrl driver (`pinctrl-mt7988.c`: `MT7988_PIN(34, "SPI2_MISO")`) and the official devicetree binding (`mediatek,mt7988-pinctrl.yaml`).
Note: GPIO 34 is also used by the BE450's First U-Boot as a recovery button (web recovery 192.168.1.1). Registering it in the DTS ensures the kernel claims the pin.
Fix 3: Incorrect memory size in DTS
The OpenWrt DTS declares 1 GB (`0x40000000`) of RAM, but the BE450 has 512 MB (`0x20000000`).
Run tested.
Signed-off-by: Semih Baskan <strst.gs@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22386
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The current CMU setup was just copied and slightly adjusted from the
SDK, lacks functionality and logic and doesn't cover all cases we need
(same in the SDK due to multiple reasons). The existing implementation
for RTL930x covers all that and can be reused for RTL931x. Previous
patches made this generic and now we can add the remaining missing
pieces to actually use it for RTL931x. This only includes
implementations for the few variant-specific actions within the
implementation, linking them properly and calling the CMU configuration.
Drop the old CMU code for RTL931x then since it's not needed anymore.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Improve the RTL931x mapper to infer the CMU page from the hardware mode
by replace unneeded with useful comments, returning a better error code
and dropping irrelevant parts.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Do some slight improvements to the generic CMU configuration for
RTL93xx. This covers several points:
- update comments to the current reality
- add fast path to avoid issues and unneeded calls
- use cached mode value instead of register read
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Generalize the RTL930x CMU configuration to support RTL931x as well.
Both implementations differ only in minor details, allowing them to
share common code and avoid duplication.
Affected functions are moved up in the code to the 93xx common area and
slightly renamed. Existing variant-specific functions are adjusted too
and assigned to the previously added SerDes operation hooks.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add new SerDes ops for CMU management to be able to share common
behavior of CMU configuration for RTL930x and RTL931x while still
covering variant specifics.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Fix naming of several functions to better reflect what they are doing.
While at it, also improve the error handling a lot, changing the return
type from void to int and actually returning errors.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Move resetting the CMU into the PLL configuration itself where the speed
is set. Since this operation is not dependent of the target SerDes and
only needs to be called if the speed changed, it fits better there.
Though the call was guarded with a 'speed_changed' before, this also
applies to actually changing the speed. This was done before anyway,
even if the speed value hasn't really changed.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add a mapper function to infer the to-be-selected PLL speed from the
desired SerDes hardware mode. This avoids having similar logic in each
CMU implementation.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Split up PLL configuration of RTL930x in the two distinct actions of
configuring the PLL itself (aka setting its speed, etc.) and selecting
which PLL is used by a SerDes.
It was found that for both RTL930x and RTL931x, PLL configuration can be
combined while selecting the PLL a SerDes uses differs and needs to be
implemented variant-specific.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Make use of the generic PLL type definition in the current CMU/PLL
configuration code for RTL930x. Assign explicit values to the fields of
the PLL type enum to tie these fields to the values that are used in
the register fields. This allows to simplify the code a bit.
Selecting the PLL to use for a SerDes shares some similarities between
RTL930x and RTL931x. While the location of the selector in the registers
is placed different, similar underlying bit semantics are used. This
allows to reuse the same plain values for both. RTL930x uses a force bit
and a selector bit, RTL931x at least uses the selector bit with the same
values for ring and LC PLL.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Make use of the generic PLL speed definition in the current CMU/PLL
configuration code for RTL930x. Assign explicit values to the field of
the PLL speed enum to tie these fields to the values that are used in
the register fields. This allows to simplify the code a bit.
Setting the actual speed selector for RTL930x was found to be similar to
RTL931x despite of different values being used since the LSB is always 1.
According to the SDK this seems to be a force bit while the other bits
are the actual value/selector that is being forced. For RTL930x,
separate the speed selection to be able to use that as common behavior
for both variants later.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Bring the PLL definitions into a proper shape. While there was already a
definition for the PLL type, a generic PLL speed definition was missing.
Introduce such a definition and adjust the naming of the existing PLL
type definition to have a better distinction and avoid conflicts. The
definitions can and should be used to make the CMU/PLL configuration
more generic and reduce the need for variant-specific definitions.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
