The functions iterating through the port statistic/counter (for
initialization or polling) use the generic name "i" for the iterator. This
makes reading the actual body of the loop cumbersome because it is not
clear that various parameters of functions are about a ports.
Suggested-by: Felix Baumann <felix.bau@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some SoC families require table access to get the HW counters. A mutex is
required for this access - which will potentially cause a sleep in the
current context. This is not always possible with .get_stats64 because it
is also called in atomic contexts.
For these SoCs, the retrieval of the current counters in .get_stats64 is
skipped and the counters are simply retrieved a lot more often from the HW.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
If an architecture doesn't need to sleep for retrieving the current
statistics from the HW, it is possible to directly retrieve the last values
from the HW when .get_stats64 is called. This avoids the stale counters
with the current refresh interval of 60 seconds.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
On many architectures, retrieving the HW counters from the switch is not
potentially sleeping. This would potentially allow these architectures to
retrieve the most recent values from the HW when .get_stats64 is called.
But because of the global mutex (which may sleep on lock), this would no
longer be possible.
Reintroduce the per port counters lock which protects from parallel
writes+reads of the non-link_stat counters. The locking is made abstract by
using helpers which identify the correct locking mechanism based on the
used read methods of the SoC.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add MIB data structures and table access routines for the RTL931X family.
These counters can now be exposed through the ethtool statistics interface.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some Realtek SoCs such as the RTL931X store MIB counters in tables rather
than registers. Unlike register reads, table access requires programming
the table control register, setting the command field to determine read or
write, and then polling for completion. This makes it necessary to
implement a separate path for table-based statistics.
Like register-based MIBs, the table-based MIBs also come in two types: STD
and PRIV which will require slightly different implementations.
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some Realtek SoCs do not expose MIB counters as simple registers. Instead,
retrieving counters may require blocking operations or take longer than a
normal register read. This makes the existing approach of direct reads
unsuitable. The existing approach uses spin locks which forbid sleeping
inside their context. But some hardware accesses methods (for example table
reads) might block (sleep).
To handle this, the MIB read path is redesigned with two levels of
locking:
* A global mutex protects updates of MIB data from the hardware. This is
necessary because reads can occur both in the polling workqueue and from
ethtool callbacks, also two user threads might call the ethtools
callbacks. A global mutex helps to avoid parallel reads of the same
hardware data. For table reads, this is not necessarily required because
they are already using a table lock. But they are the reason why
spin-locks can no longer be used (see above).
* A per-port spinlock protects the shared memory region where per-port
counters are copied. Avoids reading of half copied values in
.get_stats64()
As part of this change, MIB reads were removed from .get_stats64() since
that callback can be started from an atomic context and must never sleep
(block) in this context. A shared memory region is provided which will be
updated periodically by MIB workqueue and .get_stats64() will simply return
data from the shared memory.
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MSTI range is 0..4095 but the HW range is only supporting a lower
range - for example 0..63 for RTL930x. But the HW doesn't really need to
know the actual MSTI. It is therefore possible to use a mapping from MSTI
to HW slot to allow a larger range of MSTIs.
Since the CIST (MSTI 0) is always needed, the mapping data structure is
skipping this entry and is always keeping the HW slot 0 for CIST.
This doesn't increase the total number of MSTIs a HW supports.
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MSTP support (usually implemented by mstpd) requires from the kernel
that a VLAN can associated with an MSTI. At the moment, all these VLANs
just get the msti 0 harcoded on creation. But the
vlan_tables_read()+vlan_tables_write() helper already allow the
modification of the MSTI and only require a minimal hook to expose this
functionality.
It is also necessary to adjust the (M)STP states per MSTI and not only per
port (or for the CIST). The rtl83xx_port_stp_state_set() function was in
theory already capable to modify other MSTIs than CIST - if the msti would
not have been hardcoded to 0.
The userspace can trigger these modifications using netlink:
* (Re)associating VLANs with an MSTI:
bridge vlan global set dev <BR> vid <X> msti <Y>
* Setting the port state in a given MSTI:
bridge mst set dev <PORT> msti <Y> state <Z>
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The VLANs and their MSTIs are shared on the realtek switch HW between
bridged and unbridged ports. But the MSTI state cannot be updated for an
unbridged port via DSA. To ensure that the port is still configured
correctly after leaving a bridge, the CIST state updates via DSA must also
be propagated to the MSTI states.
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
When joining a bridge or leaving a bridge, the CIST state will
automatically be adjusted by DSA using .port_stp_state_set(). But MSTIs are
completely unhandled.
If a port is joining a bridge, the default state must be disabled. The MSTP
daemon is then responsible for adjusting the state.
If the bridge is left, the forwarding state must be enforced because VLANs
(and with this also the MSTIs assigned to them) are shared between bridged
and non-bridged ports. An unbridged port must therefore not be left in an
blocked/disabled state for a VLAN (MSTI).
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
If a VLAN doesn't have any members anymore, then it is removed and
implicitly returns back from any MSTI to CIST. The DSA layer will not
create any call to .vlan_msti_set and the driver is required to handle this
directly.
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Each SoC supports a different number of MST(I)s. The code must know this
limitation to correctly reject unsupported MSTIs or to allocate a large
enough mapping table.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The DSA port code is trying to flush associated VLANs whenever the MST
state is changed. This functionality is available on a per port+vid based
using the L2_TBL_FLUSH_CTRL which is already used for the .port_fast_age
callbacks.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The realtek DSA switch driver sets up all VLANs using CIST. It is therefore
not necessary to enforce CIST using the ST_CTRL register.
This allows us later to overwrite the MSTI of VLANs. This is necessary to
get MSTP working on RTL93xx.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
RTL838x+RTL839x both configure a default QoS behavior with a default
mapping. This also needs to be added to RTL93xx to ensure a consistent
behavior:
* Set the default mapping between DSCP and priority: prio = dscp >> 3.
* Set the default mapping between internal priority and queues
* Set uniform prioritization of queues (as with other SoCs)
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20640
Signed-off-by: Robert Marko <robimarko@gmail.com>
If link aggregation with LACP is activated, we must send out the LACP
packets on the physical port and not on a logic port. Otherwise, the per
port packets might be (rebalanced) between the different ports in a link
aggregation group.
Such rebalancing breaks 802.3ad and will leave ports in a churned state.
Fixes: 8c42e63a69 ("realtek: rtl93xx: fix incorrect destination port selection")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20728
Signed-off-by: Robert Marko <robimarko@gmail.com>
If ports of a RTL93xx switch are not added to a port matrix then they are
not used for the link aggregation. As result, communication will then just
break on non-primary interfaces.
This can be reproduced in balanced-xor and 802.3ad bandwidth mode.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20729
Signed-off-by: Robert Marko <robimarko@gmail.com>
Commit 56e9a73d0b added support for configuring the SerDes polarity for
both RTL930X and RTL931X. Based on the code in the Realtek SDK in [1]
and [2], in both cases the same register bits are set. Thus, a common
implementation was provided which worked with e.g. USXGMII or 10GBase-R
configured SerDes.
However, after further tests, a strange issue occured where it didn't
work that well for all SerDes configurations. While running fine for
10GBase-R links on two adjacent SerDes, it didn't for 1000Base-X links
on one of two adjacent SerDes with the link not being detected as a
symptom.
Diving into the SDK again revealed that the referenced implementation of
polarity configuration is (by accident or by purpose) misleading. While
[1] and [3] for RTL930X match, [2] and [4] for RTL931X actually don't.
[4] writes the bits for the 1G polarity setting on different background
SerDes, thus in another frontend page.
Split implementations for RTL930X and RTL931X again and adjust the one
for RTL931X according to [4]. This resolves the issues with 1000Base-X
behavior.
[1] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9300.c (L1384)
[2] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9310.c (L3479)
[3] 69d2890a2e/sources/rtk-xgs1210/src/dal/longan/dal_longan_construct.c (L2246)
[4] 69d2890a2e/sources/rtk-xgs1210/src/dal/mango/dal_mango_construct.c (L1550)
Fixes: 56e9a73d0b ("realtek: pcs: rtl93xx: provide proper SerDes polarity
configuration")
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20767
Signed-off-by: Robert Marko <robimarko@gmail.com>
The name "is_lagmember" implies that the port is part of a LAG. But this
information is already stored in lagmembers. In reality, it is stored the
non-primary LAG members. Renaming it accordingly, makes the code a lot more
readable
Also the type (u32 array) looks like it would contain some kind of large id
(like the group ID). But it only stores a single bit. It is more appropriate
to just use a single bit per port.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The names of the LAG variables in struct rtl838x_switch_priv are not self
explaining. They are even suggesting that they are dealing with information
which are actually stored in a different variable. As first step, document
their meaning.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
There is no need to check conditions in rtl83xx_lag_add()/rtl83xx_lag_del()
when they are already checked in
rtl83xx_port_lag_join()/rtl83xx_port_lag_leave().
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
It is not necessary to have a private LAG id allocation when the shared DSA
code already provides the complete infrastructure for it.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The DSA code is responsible to inform the driver about link aggregation
changes. Having a second one which behaves slightly different makes the
whole process fragile and creates hard to debug problems.
It also complicates the code because the secondary event handler can also
not rely on shared DSA state to handle things like LAG ID.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The rtl83xx_lag_can_offload() function always returned an error because
ds->num_lag_ids was never set. This basically disabled the DSA lag
configuration completely.
Drop the private n_lag variable and instead use the DSA specific one. This
ensures that all the code always has the same reference for the number of
LAGs.
Fixes: 32e5b5ee6b ("realtek: Add Link Aggregation (aka trunking) support")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Th function to set the mangement frames receive actions is only used in the
SoC specific files. They can therefore be kept local without any
declaration in headers.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20704
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The code for the RTL930x management action configuration was cleaned up
significantly for commit 75fe6b2d0b ("realtek: rtl930x: Add support for
trapping management frames"). Sync these changes to RTL931x to make it
easier to extend both implementations.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20704
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Allow to configure SerDes polarity in device tree. To achieve this, add
new device tree properties that can be set in the device tree definition
of the SerDes, are read by the PCS driver during probe and are applied
upon SerDes setup.
This may be required for supporting new devices as the SerDes polarity
is usually subject to the vendors board design and defined in the
hardware profile (HWP) in the SDK. Most importantly, it is quite an
important step towards being able to setup everything on our own instead
of relying on the bootloader.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20648
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The configuration code for RTL930X already provides setting the SerDes
TX and RX PN polarity. This is covered by a function called
'..._sds_mac_link_config'. But despite its name, this function only sets
the SerDes polarity and nothing more.
Moreover, this was called always with 'not inverted' in the SerDes setup
code and thus not really allowing to be configured.
At first, streamline the SerDes polarity configuration code. Rename the
function to reflect what it actually does instead of giving the
impression of doing more. Improve the implementation of this for better
readability.
As the implementation, page, register, bits, etc. are exactly the same
for both RTL930X and RTL931X (compare [1] and [2]), move and name it
accordingly so we can also add support for RTL931X.
[1] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9300.c (L1384)
[2] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9310.c (L3479)
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20648
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL930x and RTL931x have an ingress and egress bandwidth controller for
each port. They can can be used to reduce the throughput for each port.
They can be programmed via the the DSA flower offloading capabilities. Only
a limited functionality (bytes based rate limiter for ingress/egress) is
supported.
With kmod-sched-act-police, kmod-sched-flower and tc installed, each port
can have its ingress/egress rate limit applied in hardware using:
# tc qdisc del dev lan1 clsact
tc qdisc add dev lan1 clsact
tc filter add dev lan1 ingress flower skip_sw action police rate 100mbit burst 64k conform-exceed drop
tc filter add dev lan1 egress flower skip_sw action police rate 150mbit burst 64k conform-exceed drop
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20663
Signed-off-by: Robert Marko <robimarko@gmail.com>
On RTL930x, each SerDes pair shares a set of PLLs with different
capabilities (LC PLL: 1G/2.5G/10G, ring PLL: 1G/2.5G). In principle,
this allows any combination of speeds on a SerDes pair. However, it
creates a special case when trying to configure a SerDes for 10G while
the LC PLL is already in use at a slower speed for the neighbor SerDes.
The current implementation just gives up in that case. Instead, free up
the LC PLL by reconfiguring the neighbor SerDes to the ring PLL.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/20568
Signed-off-by: Robert Marko <robimarko@gmail.com>
It is not necessary to have two different family_id checks directly after
another. It is simpler to just combine both into one.
Suggested-by: Álvaro Fernández Rojas <noltari@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20637
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
The rtl838x_rate_control_init() and rtl839x_rate_control_init() functions
were never called because the rtl83xx_setup_qos() always returned after the
QoS configuration
Fixes: dc9cc0d3e2 ("realtek: add QoS and rate control")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20637
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
After having moved RTL93XX SerDes configuration from PHY to PCS driver,
the DSA driver doesn't need to know about SerDes explicitly anymore.
Although RTL83XX SerDes is still partly managed within the DSA driver,
it doesn't make use of the sds_num property/field. RTL93XX was the only
user of this right now.
Thus, we can just remove the remaining 'sds_num' code which doesn't
serve any purpose anymore.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93XX SerDes is entirely managed through the PCS driver and not
treated as PHYs anymore. Thus, remove the leftovers from the DSA driver.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
Drop the now unused SerDes code for RTL930X from rtl83xx-phy driver as
the SerDes is completely managed by the PCS driver.
This marks a breaking point because RTL930X SerDes is no longer treated
as a regular PHY device.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
When Realtek SerDes is completely handled by PCS, it is not treated as
a regular PHY anymore. Thus, we should be able to drop the currently
used pseudo-PHYs and phy-handles for ports which just use the SerDes as
PCS but have no PHY attached.
Allow to drop the phy-handle from switch port definitions if there is a
pcs-handle defined by relaxing several checks in the DSA driver.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
Check for and handle an error which may be returned by rtpcs_create in
various cases.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
The code to add bootstrapping for 10G-QXGMII on RTL930X broke the only
devices which are using 10G-QXGMII on RTL930X (Plasma Cloud PSX8+PSX10) in
OpenWrt. It is currently unknown what other changes are pending to get this
correctly working. But both the `rtpcs_930x_sds_usxgmii_config()` call and
the write of the "magic" SerDes values in the patching process break the
SerDes connected to the RTL8224 PHYs.
The Plasma Cloud PSX8+PSX10 devices get their RTL8224 and the 10G-QXGMII
SerDes bootstrapped directly by u-boot.
Fixes: dca20f91ea ("realtek: add serdes patch for 10G_QXGMII")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20588
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix regression from back when support for RTL930x was added.
While at it replace 0x8000 by BIT(15).
Fixes: 27029277f9
Tested-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Felix Baumann <felix.bau@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20549
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove SerDes initialization/configuration calls from the DSA driver in
'rtl93xx_phylink_mac_config' and let our PCS driver setup the SerDes now
that the driver is able to do that.
Adjust some details in rtl93xx_phylink_mac_config to ensure the MAC is
properly disabled MAC before configuring the SerDes. This was done
within the SerDes code before.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use regmap to access registers in the global register space so we don't
have to use the old macros sw_r32/sw_w32 anymore.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
Import SerDes configuration code from PHY driver into the PCS driver.
Only do mandatory adjustments, rename the function to adhere to the
naming scheme, adjust all SerDes access calls.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
In Realtek implementation USXGMII is divided in submodes:
- USXGMII_SX: 10G single link, equivalent of PHY_INTERFACE_MODE_USXGMII
- USXGMII_DX: 10G two links (2*5G ?),
- USXGMII_QX: 10G four links, presumably 4*2.5G, used with the RTL8224,
equivalent of PHY_INTERFACE_MODE_10G_QXGMII.
This CL adds the 10_GQXGMII modes to the RTL930x implementation. In
particular the "mode set" function is extended to support both simple
mode set, and force mode set depending on the mode according to
dal_longan_sds_mode_set [1].
[1] https://github.com/ddejean/dms-1250-oss-release/blob/main/sdk/sdk_rtk_switch/rtk-sdk/src/dal/longan/dal_longan_sds.c#L1746
Signed-off-by: Damien Dejean <dam.dejean@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20472
Signed-off-by: Robert Marko <robimarko@gmail.com>
Since ddf94f7489 and 4a5de35dba, a SerDes is configured by the PCS
driver. All code from PHY and DSA related to this has been imported and
adjusted into the PCS driver. Thus, remove the unused code from the PHY
driver now.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20494
Signed-off-by: Robert Marko <robimarko@gmail.com>
L3 Offloading caused DHCP packets to be dropped at hardware level
And potentially buggy route implementation can cause a crash
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20208
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL931x is not supporting L3 offloading at the moment. To avoid crashes
when using this switch, simply disable L3 offloading completely.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20208
Signed-off-by: Robert Marko <robimarko@gmail.com>
Originally, phylink_mac_config first disabled the MAC, then triggered
the SerDes setup and then re-enabled MAC. SerDes setup has been moved to
the PCS driver now but pcs_config is called AFTER phylink_mac_config by
phylink subsystem.
Thus, just disable the MAC in phylink_mac_config. After PCS has setup
the SerDes, the MAC should be properly brought up in a mac_link_up call
coming from the phylink subsystem.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
