It is not necessary to have two different family_id checks directly after
another. It is simpler to just combine both into one.
Suggested-by: Álvaro Fernández Rojas <noltari@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20637
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
The rtl838x_rate_control_init() and rtl839x_rate_control_init() functions
were never called because the rtl83xx_setup_qos() always returned after the
QoS configuration
Fixes: dc9cc0d3e2 ("realtek: add QoS and rate control")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20637
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
This device is very similar to the already supported XGS1210-12 A1. For
now, only revision A1 is supported (not marked on the label).
Hardware:
- RTL9302B SoC
- 16 MiB NOR flash
- 128 MiB DDR3 SDRAM
- 8x 1G RJ45 (RTL8218D)
- 2x 2.5G RJ45 (2x RTL8226)
- 2x SFP+ (supporting 1G/2.5G/10G)
- 3.3V UART serial (115200 baud 8N1) on the right side of the case
(from bottom to top: GND, RX, TX, VCC)
It is originally an unmanaged switch, so there are a few differences:
- No reset button
- Different partition layout: There is some reserved space in the middle
of the flash which might be used by the bootloader for flash testing.
The remaining space in between is used for OpenWrt using mtd-concat.
The largest contiguous area is at the beginning, allowing a maximum
kernel size of 7 MiB.
- No individual MAC address: This device ships with an empty U-Boot
environment. When an OpenWrt squashfs image is booted for the first
time, a random MAC address will be written to the environment (but
only if the environment has been initialized from the bootloader
before and contains the default MAC address).
Steps to boot initramfs image via network:
- Configure a TFTP server to provide the OpenWrt initramfs image
- Connect to device using serial (see hardware information above)
- Power on the device and enter U-Boot using Esc when prompted
- Run the following commands (adjust as necessary):
# rtk network on
# tftpboot 0x84f00000 192.168.1.100:openwrt-xgs1010-initramfs.bin
# bootm
Installation on flash:
- Boot initramfs image as described above
- Now is a good time to create a backup of all flash partitions! You'll
need this if you want to revert to the unmanaged factory firmware at
some point.
- Use sysupgrade to install OpenWrt
- After restart enter U-Boot again and set the boot command:
# setenv bootcmd 'rtk network on; bootm 0xb4900000'
# saveenv
# run bootcmd
Note: The command "rtk network on" is only needed because the drivers
currently rely on some setup by the bootloader (without this the RJ45
ports don't work). If the drivers improve in the future, it should be
removed (i.e. change the boot command to "bootm 0xb4900000").
Reverting to factory firmware:
- Write back your backup of the firmware partition (or write just the
fwconcat1 partition, and erase the other two fwconcat partitions)
- Change the boot command back to "boota" (or just erase the u-boot-env
partition so the default gets used)
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/20469
Signed-off-by: Robert Marko <robimarko@gmail.com>
This is a preparation for adding support for XGS1010-12, which is almost
identical to XGS1210-12, with some small differences (partition layout,
missing reset key).
In addition to moving the common parts to a new file, also simplify the
definition of the 2.5G PHYs to reduce duplication. With this change, the
revision-specific files only have to specify the SMI addresses.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/20469
Signed-off-by: Robert Marko <robimarko@gmail.com>
After having moved RTL93XX SerDes configuration from PHY to PCS driver,
the DSA driver doesn't need to know about SerDes explicitly anymore.
Although RTL83XX SerDes is still partly managed within the DSA driver,
it doesn't make use of the sds_num property/field. RTL93XX was the only
user of this right now.
Thus, we can just remove the remaining 'sds_num' code which doesn't
serve any purpose anymore.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93XX SerDes is entirely managed through the PCS driver and not
treated as PHYs anymore. Thus, remove the leftovers from the DSA driver.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
Drop the now unused SerDes code for RTL930X from rtl83xx-phy driver as
the SerDes is completely managed by the PCS driver.
This marks a breaking point because RTL930X SerDes is no longer treated
as a regular PHY device.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93XX reached the point where the SerDes' are no longer treated as
regular PHYs. Instead, they are managed by the dedicated PCS driver.
Thus, all device tree definitions should follow this change.
Remove the pseudo-PHYs for the SerDes (so far usually defined with macro
INTERNAL_PHY) and corresponding 'phy-handle's from all SFP ports. This
removes a long-lasting confusion from our Realtek driver(s).
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
When Realtek SerDes is completely handled by PCS, it is not treated as
a regular PHY anymore. Thus, we should be able to drop the currently
used pseudo-PHYs and phy-handles for ports which just use the SerDes as
PCS but have no PHY attached.
Allow to drop the phy-handle from switch port definitions if there is a
pcs-handle defined by relaxing several checks in the DSA driver.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
Check for and handle an error which may be returned by rtpcs_create in
various cases.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20577
Signed-off-by: Robert Marko <robimarko@gmail.com>
The code to add bootstrapping for 10G-QXGMII on RTL930X broke the only
devices which are using 10G-QXGMII on RTL930X (Plasma Cloud PSX8+PSX10) in
OpenWrt. It is currently unknown what other changes are pending to get this
correctly working. But both the `rtpcs_930x_sds_usxgmii_config()` call and
the write of the "magic" SerDes values in the patching process break the
SerDes connected to the RTL8224 PHYs.
The Plasma Cloud PSX8+PSX10 devices get their RTL8224 and the 10G-QXGMII
SerDes bootstrapped directly by u-boot.
Fixes: dca20f91ea ("realtek: add serdes patch for 10G_QXGMII")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20588
Signed-off-by: Robert Marko <robimarko@gmail.com>
Commits d205878ede and 46cf10771a relabeled the supported Zyxel devices
from v1/v2 to A1/B1, but board setup files were overlooked.
Fixes: d205878ede ("rtl838x: rename GS1900 series v1/v2 to A1/B1")
Fixes: 46cf10771a ("rtl839x: rename GS1900 series v1/v2 to A1/B1")
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Link: https://github.com/openwrt/openwrt/pull/20590
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix regression from back when support for RTL930x was added.
While at it replace 0x8000 by BIT(15).
Fixes: 27029277f9
Tested-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Felix Baumann <felix.bau@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20549
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove SerDes initialization/configuration calls from the DSA driver in
'rtl93xx_phylink_mac_config' and let our PCS driver setup the SerDes now
that the driver is able to do that.
Adjust some details in rtl93xx_phylink_mac_config to ensure the MAC is
properly disabled MAC before configuring the SerDes. This was done
within the SerDes code before.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use regmap to access registers in the global register space so we don't
have to use the old macros sw_r32/sw_w32 anymore.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
Import SerDes configuration code from PHY driver into the PCS driver.
Only do mandatory adjustments, rename the function to adhere to the
naming scheme, adjust all SerDes access calls.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
In Realtek implementation USXGMII is divided in submodes:
- USXGMII_SX: 10G single link, equivalent of PHY_INTERFACE_MODE_USXGMII
- USXGMII_DX: 10G two links (2*5G ?),
- USXGMII_QX: 10G four links, presumably 4*2.5G, used with the RTL8224,
equivalent of PHY_INTERFACE_MODE_10G_QXGMII.
This CL adds the 10_GQXGMII modes to the RTL930x implementation. In
particular the "mode set" function is extended to support both simple
mode set, and force mode set depending on the mode according to
dal_longan_sds_mode_set [1].
[1] https://github.com/ddejean/dms-1250-oss-release/blob/main/sdk/sdk_rtk_switch/rtk-sdk/src/dal/longan/dal_longan_sds.c#L1746
Signed-off-by: Damien Dejean <dam.dejean@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20472
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix the GPIO assignment of RX-LOS and TX-DISABLE for all SFP ports. Both
were actually swapped when adding support for the device. Apparently,
this didn't cause any issues.
Fixes: 62d50fb196
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20532
Signed-off-by: Robert Marko <robimarko@gmail.com>
Since ddf94f7489 and 4a5de35dba, a SerDes is configured by the PCS
driver. All code from PHY and DSA related to this has been imported and
adjusted into the PCS driver. Thus, remove the unused code from the PHY
driver now.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20494
Signed-off-by: Robert Marko <robimarko@gmail.com>
Allows us a bit more headroom flash wise and access to more recent
compression algorithms.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Link: https://github.com/openwrt/openwrt/pull/20445
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
L3 Offloading caused DHCP packets to be dropped at hardware level
And potentially buggy route implementation can cause a crash
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20208
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL931x is not supporting L3 offloading at the moment. To avoid crashes
when using this switch, simply disable L3 offloading completely.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20208
Signed-off-by: Robert Marko <robimarko@gmail.com>
Originally, phylink_mac_config first disabled the MAC, then triggered
the SerDes setup and then re-enabled MAC. SerDes setup has been moved to
the PCS driver now but pcs_config is called AFTER phylink_mac_config by
phylink subsystem.
Thus, just disable the MAC in phylink_mac_config. After PCS has setup
the SerDes, the MAC should be properly brought up in a mac_link_up call
coming from the phylink subsystem.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Remove SerDes initialization/configuration calls from the DSA driver in
'rtl931x_phylink_mac_config' and let our PCS driver setup the SerDes now
that the driver is able to do that.
pcs_config of the PCS driver is automatically called by phylink, thus
there's no need to call it on our own.
Note that in rtl931x_phylink_mac_config the MAC is enabled before
pcs_config is called. While this seems to work, it isn't good and needs
to be fixed.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
In rtpcs_931x_setup_serdes, quit early on USXGMII mode. This restores
the behaviour introduced in c18476d0c5 to prevent the current buggy
procedure to destroy a working configuration established by U-Boot
before.
Also include the valuable comment from the code to keep the information.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Adjust the SerDes page numbers to account for the different mapping used
by 'mdio-realtek-otto' and 'mdio-realtek-otto-serdes' drivers.
While importing the SerDes configuration code from PHY driver to PCS
driver, all helper calls to access the SerDes registers had to be
adjusted to use the proper helpers within the PCS driver. However, there
is one important implication of this: 'mdio-realtek-otto' and
'mdio-realtek-otto-serdes' use a slightly different page mapping.
While the old helpers in 'mdio-realtek-otto' used a page mapping of
0x00/0x100/0x200, 'mdio-realtek-otto-serdes' uses a mapping of
0x00/0x40/0x80 to provide consumers with the ability to only operate on
frontend SerDes. Thus, all page numbers > 63/0x3f have to be adjusted
like the following:
before: rtsds_931x_write_field(sds, 0x101, ... // old helper calls
after: rtpcs_sds_write(ctrl, sds, 0x41, ...
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Replaces the "old" way of accessing registers using the macros
sw_r32/sw_w32 from mach-rtl83xx.h. The "new" way to access register is
through the regmap API.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Let's start this transition with RTL931X.
Import all functions starting with 'rtl931x_' or 'rtsds_931x' from PHY
driver into the PCS driver, rename all functions to match a common
naming scheme and adjust signature, helper calls and function calls
accordingly to make it work within the PCS driver.
This is just copy&paste and tries to do only mandatory adjustments. The
code will be refactored in succeeding commits.
Also remove 'unused' attribute from helpers as they are used now.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
rev B1 is identical to rev A1 except for different PHYs on the 2.5gbps ports (lan9 and lan10)
Both revisions of xgs1210-12 are also switched to use rt-loader to avoid
problems due to overwriting the compressed image in memory when flashing
with the oem firmware (and also to save flash space with respect to gzip
compression)
Signed-off-by: Josh Bendavid <joshbendavid@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20161
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The DSA driver must flush the HW FDB when a port changes from
learning/forwarding to disabled/blocking/listening.
But the implementation for RTL931x was writing the port information
starting at bit 11 (bit 11 of the second 32-bit L2_TBL_FLUSH_CTRL
register). But this offset is the AGG_VID and not the port. The actual
position is 43 (bit 11 of the first register).
As result, the FDB was always only flushed for the port 0 and not for the
selected port.
Fixes: 9ed6097054 ("realtek: Add HW support for RTL931X for PIE, L2 and STP aging")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20422
Signed-off-by: Robert Marko <robimarko@gmail.com>
BPDU frames like STP must be processed by each switch (bridge) which
supports STP. It must not be forwarded to avoid confusing the STP state of
other STP participants. It is essential to be an active participant of STP.
The software bridge automatically takes care of forwarding the BPDUs to
other ports when STP is disabled and the hardware switch should not
interfere.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20414
Signed-off-by: Robert Marko <robimarko@gmail.com>
Right now the phylink capability function enables 2.5G and 10G modes on
Maple and Cypress, which they mostly (other than two SERDES on Cypress)
don't support. This causes these modes to be selected and break the link
as they are not supported by hardware.
I looked into doing this properly, but it cannot just be done based on
SoC, but needs to take the whole topology into account as a given MAC
might have very different capabilities depending on what SERDES are
assigned to it. So for now just use 1G and QSGMII for RTL83xx and 10G
for RTL93xx. This mostly works, except it will downgrade some 10G links
on RTL839x, but since there are also 1G SFPs on these this cannot be
solved without fully accounting for the global MAC and SERDES
configuration.
So this makes all of the 1G SFP slots work again, while keeping most of
the 10G SFP+ slots working at 10G with minimal changes.
Signed-off-by: Lorenz Brun <lorenz@brun.one>
Link: https://github.com/openwrt/openwrt/pull/20374
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
If the devicetree contains the appropriate nodes to configure the MAC
addresses for each physical DSA port, then these MAC addresses must be used
in OpenWrt and not some automatically generated ones. Otherwise the device
often ends up with addresses which are locally administered and not
matching any expected port-to-MAC scheme.
Devices which only get the MAC address for eth0 must still auto-generate
these MAC addresses until the devicetree was updated to also include the
correct ones.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20241
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
If the lan_mac cannot be found, it is still used (as empty string) in
various operations. This is not valid and other 02_network scripts checking
for a non-empty string before using it. This should also be adopted for the
realtek 02_network.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20241
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Having everything in a big script without any structure makes it
unnecessary hard to get an overview or modify it without triggering
unexpected side effects.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20241
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The preferred prefix for the Realtek DSA driver code is "rtldsa" and no
longer "rtl83xx". This makes sure that the different drivers have
non-conflicting prefixes and because of this non-conflicting function
names.
Suggested-by: Felix Baumann <felix.bau@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL930x and the RTL931x SoC families share the same struct
dsa_switch_ops. This should be represented in the name of the object.
Suggested-by: Felix Baumann <felix.bau@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
If two ports are in isolation mode then these ports are not supposed to be
able to communicate between each other. This can be achieved in the realtek
switch by removing the other isolated port(s) from the port list of an
isolated port.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
The realtek driver is now in full control of the port matrix. It doesn't
need to rely on the current state of the HW to adjust it. The new port
matrix is calculated automatically using rtldsa_update_port_member() and
then written to the registers/tables.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
It is not necessary to read the back the current port members for a
specific port for enabling/disabling a port. All these members which are
expected to be in the HW port matrix of an active port are already stored
in the port specific member "pm".
And when a port is disabled, the port must no longer forwarding traffic to
any other port. Just writing 0 to the members is therefore good enough and
no read-back of the old HW state is necessary.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
The leave and join callbacks for DSA were using their own implementation of
the port member handling code. This makes the implementation of additional
functionality based on the port member matrix complicated because it needs
to be implemented in both places and also in the new code path for the
introduced feature.
By sharing this code, it is much easier to guarantee that all code paths
behave the same. This approach is already implemented by other DSA drivers
like qca8k, mt7530 or ksz.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add a callback for a serdes setup function to rtpcs_cfg to allow each
SoC variant to define its own SerDes setup routine.
Call the setup_serdes operation in pcs_config if it is defined.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20352
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add more SerDes access helpers for the upcoming code import from PHY
driver. There, similar helpers are used to read and write full SerDes
registers or only parts of them (aka bitfields).
The helpers are expected to replace the following used in PHY SerDes
code:
- rtl9300_sds_field_r
- rtl9300_sds_field_w
- rtsds_931x_read
- rtsds_931x_read_field
- rtsds_931x_write
- rtsds_931x_write_field
Mark the helpers as unused for now to make the compiler happy. This will
be removed as soon as they are used.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20352
Signed-off-by: Robert Marko <robimarko@gmail.com>
The A1 and B1 devices are largely the same. The differences
seem to be:
- RTL8218D (A1) vs RTL8218E (B1) PHY for the eight 1 Gbps TP ports
- Aquantia (A1) vs RTL8261N (B1) PHY for the three 10 Gbps TP ports
RTL8218D/E share the same driver and support was added already by
commit c8c187f0f0 ("realtek: add support for RTL8218E").
The RTL8261N is also already supported but it's located at
different addresses compared to the A1 device. This requires
the device tree to be split. As a result, the devices are require
different images.
I found the smi addresses on the forum:
https://forum.openwrt.org/t/support-for-rtl838x-based-managed-switches/57875/3622
And I can conform on my B1 device that this is working.
Co-developed-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: Thomas Martitz <thomas.martitz@mailbox.org>
Link: https://github.com/openwrt/openwrt/pull/20150
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
There are switches which share the same overall hardware design but remove
just a couple of components for the low cost variant. For example, a 8+2
(ethernet+SFP) switch might have a low cost variant which only has 8
ethernet ports. In this case, the PCB will be shared but components for SFP
will just be dropped.
The LED shift registers will be the same between the two switches but the
ports are different. But since the rtl930x_led_init code is trying to
calculate the number of LEDs using the LED ports, the ethernet status ports
will then suddenly be shifted by two ports.
It is therefore necessary to have a mechanism to overwrite the detection of
the ethernet ports in the LED initialization and force some ports to
"virtually there" for the LED controller.
This functionality was already implemented for Plasma Cloud PSX8 (RTL930x)
but some devices using RTL931x might also benefit from a similar feature.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20300
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The LED sets must be configured before per-port LEDs are actually assigned.
At the same time, the LED set configuration was basically unreadable and
the RTL930x from commit 2cfb1ecf10 ("rtl930x: Rework per port LED
configuration") does a better job. Instead of moving the old implementation
around, just adopt the one from RTL930x.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20300
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
