From f5ec3f2df21ff7e41f631b72b35b786dbbee99ff Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Mon, 9 Mar 2026 10:50:44 +0100 Subject: [PATCH] realtek: dts: normalize Zyxel XGS1x10 DTS The Zyxel XGS1x10 DTS overzealously tries to avoid redundancies. For this the phy24/phy25 definitions were split into a common and a device specific part. Understanding how these phys are defined is therefore a little bit tricky. Add a little bit of redundancy to make the definitions easier to read and understand in a single location. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/22236 Signed-off-by: Robert Marko --- .../dts/rtl9302_zyxel_xgs1010-12-a1.dts | 20 +++++++++++++------ .../dts/rtl9302_zyxel_xgs1210-12-a1.dts | 20 +++++++++++++------ .../dts/rtl9302_zyxel_xgs1210-12-b1.dts | 16 +++++++++++---- .../dts/rtl9302_zyxel_xgs1x10-12-common.dtsi | 18 ----------------- 4 files changed, 40 insertions(+), 34 deletions(-) diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts index 513f217170..c136437bba 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts @@ -103,12 +103,20 @@ }; }; -&phy24 { - realtek,smi-address = <8>; - enet-phy-pair-order = <1>; +&mdio_bus1 { + phy24: ethernet-phy@24 { + reg = <24>; + realtek,smi-address = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <1>; + }; }; -&phy25 { - realtek,smi-address = <9>; - enet-phy-pair-order = <1>; +&mdio_bus2 { + phy25: ethernet-phy@25 { + reg = <25>; + realtek,smi-address = <9>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <1>; + }; }; diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts index 2f8ea1b9fa..3f32b9b640 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts @@ -8,12 +8,20 @@ model = "Zyxel XGS1210-12 A1 Switch"; }; -&phy24 { - realtek,smi-address = <8>; - enet-phy-pair-order = <1>; +&mdio_bus1 { + phy24: ethernet-phy@24 { + reg = <24>; + realtek,smi-address = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <1>; + }; }; -&phy25 { - realtek,smi-address = <9>; - enet-phy-pair-order = <1>; +&mdio_bus2 { + phy25: ethernet-phy@25 { + reg = <25>; + realtek,smi-address = <9>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <1>; + }; }; diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts index 2a9eeda64a..2cff52ffaa 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts @@ -8,10 +8,18 @@ model = "Zyxel XGS1210-12 B1 Switch"; }; -&phy24 { - realtek,smi-address = <1>; +&mdio_bus1 { + phy24: ethernet-phy@24 { + reg = <24>; + realtek,smi-address = <1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; }; -&phy25 { - realtek,smi-address = <2>; +&mdio_bus2 { + phy25: ethernet-phy@25 { + reg = <25>; + realtek,smi-address = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; }; diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi b/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi index a13d953374..a5fe740aef 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi +++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi @@ -124,24 +124,6 @@ }; }; -&mdio_bus1 { - phy24: ethernet-phy@24 { - reg = <24>; - compatible = "ethernet-phy-ieee802.3-c45"; - // Disabled because we do not know how to bring up again - // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; -}; - -&mdio_bus2 { - phy25: ethernet-phy@25 { - reg = <25>; - compatible = "ethernet-phy-ieee802.3-c45"; - // Disabled because we do not know how to bring up again - // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; -}; - &switch0 { ethernet-ports { #address-cells = <1>;