Marek Vasut ffb8b66ea8 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6 ... Factor out center_dq_windows(), which is common code between stage 2 and stage 3 of the calibration again and cater for the minor differences. Signed-off-by: Marek Vasut <marex@denx.de>		2015-08-08 14:14:22 +02:00
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altera	ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6	2015-08-08 14:14:22 +02:00
fsl	drivers/ddr/fsl: Adjust bstopre value	2015-08-03 12:06:38 -07:00
marvell	arm: mvebu: a38x: Use correct PEX register access macros	2015-07-23 10:39:25 +02:00