Romain Perier fefe9d06bd rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE ... RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit 0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and introduces random delays and data lose. This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE with the right shift. Signed-off-by: Romain Perier <romain.perier@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>		2017-06-07 21:30:48 -06:00
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asm	rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE	2017-06-07 21:30:48 -06:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00