mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
d96ce76277
Enabling spi dma driver for ipq40xx. This patch also enables rx and tx pipe configurable from dts. Change-Id: Id6009f6e9863ab2cdf8b105461d62aa68e3d004b Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
301 lines
9.9 KiB
C
301 lines
9.9 KiB
C
/*
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* Register definitions for the IPQ40XX QUP-SPI Controller
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* Copyright (c) 2015, 2017 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IPQ_SPI_BAM_H_
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#define _IPQ_SPI_BAM_H_
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#define QUP0_BASE 0x78b5000
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#define QUP1_BASE 0x78b6000
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#define BLSP0_BAM_BASE 0x7884000
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#define BLSP0_QUP_REG_BASE (QUP0_BASE + 0x00000000)
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#define BLSP1_QUP_REG_BASE (QUP1_BASE + 0x00000000)
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#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300)
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#define BLSP1_SPI_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000300)
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#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304)
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#define BLSP1_SPI_IO_CONTROL_REG (BLSP1_QUP_REG_BASE + 0x00000304)
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#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308)
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#define BLSP1_SPI_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x00000308)
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#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310)
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#define BLSP1_SPI_DEASSERT_WAIT_REG (BLSP1_QUP_REG_BASE + 0x00000310)
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#define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c)
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#define BLSP1_SPI_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x0000030c)
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#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000)
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#define BLSP1_QUP_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000000)
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#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c)
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#define BLSP1_QUP_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x0000001c)
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#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020)
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#define BLSP1_QUP_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x00000020)
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#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028)
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#define BLSP1_QUP_OPERATIONAL_MASK (BLSP1_QUP_REG_BASE + 0x00000028)
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#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018)
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#define BLSP1_QUP_OPERATIONAL_REG (BLSP1_QUP_REG_BASE + 0x00000018)
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#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008)
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#define BLSP1_QUP_IO_MODES_REG (BLSP1_QUP_REG_BASE + 0x00000008)
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#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004)
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#define BLSP1_QUP_STATE_REG (BLSP1_QUP_REG_BASE + 0x00000004)
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#define BLSP0_QUP_INPUT_FIFOc_REG(c) \
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(BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c))
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#define BLSP1_QUP_INPUT_FIFOc_REG(c) \
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(BLSP1_QUP_REG_BASE + 0x00000218 + 4 * (c))
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#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \
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(BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c))
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#define BLSP1_QUP_OUTPUT_FIFOc_REG(c) \
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(BLSP1_QUP_REG_BASE + 0x00000110 + 4 * (c))
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#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200)
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#define BLSP1_QUP_MX_INPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000200)
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#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100)
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#define BLSP1_QUP_MX_OUTPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000100)
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#define BLSP0_QUP_MX_READ_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000208)
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#define BLSP1_QUP_MX_READ_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000208)
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#define BLSP0_QUP_MX_WRITE_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000150)
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#define BLSP1_QUP_MX_WRITE_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000150)
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#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c)
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#define BLSP1_QUP_SW_RESET_REG (BLSP1_QUP_REG_BASE + 0x0000000c)
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#define QUP_STATE_VALID_BIT 2
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#define QUP_STATE_VALID 1
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#define QUP_STATE_MASK 0x3
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#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8)
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#define QUP_CONFIG_MINI_CORE_SPI (1 << 8)
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#define QUP_CONF_INPUT_MSK (1 << 7)
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#define QUP_CONF_INPUT_ENA (0 << 7)
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#define QUP_CONF_NO_INPUT (1 << 7)
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#define QUP_CONF_OUTPUT_MSK (1 << 6)
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#define QUP_CONF_OUTPUT_ENA (0 << 6)
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#define QUP_CONF_NO_OUTPUT (1 << 6)
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#define QUP_STATE_RUN_STATE 0x1
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#define QUP_STATE_RESET_STATE 0x0
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#define QUP_STATE_PAUSE_STATE 0x3
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#define SPI_BIT_WORD_MSK 0x1F
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#define SPI_8_BIT_WORD 0x07
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#define LOOP_BACK_MSK (1 << 8)
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#define NO_LOOP_BACK (0 << 8)
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#define SLAVE_OPERATION_MSK (1 << 5)
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#define SLAVE_OPERATION (0 << 5)
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#define CLK_ALWAYS_ON (0 << 9)
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#define MX_CS_MODE (1 << 8)
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#define NO_TRI_STATE (1 << 0)
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#define FORCE_CS_MSK (1 << 11)
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#define FORCE_CS_EN (1 << 11)
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#define FORCE_CS_DIS (0 << 11)
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#define OUTPUT_BIT_SHIFT_MSK (1 << 16)
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#define OUTPUT_BIT_SHIFT_EN (1 << 16)
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#define INPUT_BLOCK_MODE_MSK (0x03 << 12)
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#define INPUT_BLOCK_MODE (0x01 << 12)
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#define OUTPUT_BLOCK_MODE_MSK (0x03 << 10)
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#define OUTPUT_BLOCK_MODE (0x01 << 10)
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#define INPUT_BAM_MODE (0x3 << 12)
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#define OUTPUT_BAM_MODE (0x3 << 10)
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#define PACK_EN (0x1 << 15)
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#define UNPACK_EN (0x1 << 14)
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#define PACK_EN_MSK (0x1 << 15)
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#define UNPACK_EN_MSK (0x1 << 14)
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#define OUTPUT_SERVICE_MSK (0x1 << 8)
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#define INPUT_SERVICE_MSK (0x1 << 9)
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#define OUTPUT_SERVICE_DIS (0x1 << 8)
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#define INPUT_SERVICE_DIS (0x1 << 9)
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#define SPI_INPUT_FIRST_MODE (1 << 9)
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#define SPI_IO_CONTROL_CLOCK_IDLE_HIGH (1 << 10)
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#define QUP_DATA_AVAILABLE_FOR_READ (1 << 5)
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#define QUP_OUTPUT_FIFO_NOT_EMPTY (1 << 4)
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#define OUTPUT_SERVICE_FLAG (1 << 8)
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#define INPUT_SERVICE_FLAG (1 << 9)
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#define QUP_OUTPUT_FIFO_FULL (1 << 6)
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#define SPI_INPUT_BLOCK_SIZE 4
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#define SPI_OUTPUT_BLOCK_SIZE 4
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#define MSM_QUP_MAX_FREQ 51200000
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#define MAX_COUNT_SIZE 0xffff
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#define SPI_RESET_STATE 0
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#define SPI_RUN_STATE 1
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#define SPI_CORE_RESET 0
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#define SPI_CORE_RUNNING 1
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#define SPI_MODE0 0
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#define SPI_MODE1 1
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#define SPI_MODE2 2
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#define SPI_MODE3 3
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#define BLSP0_SPI 0
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#define BLSP1_SPI 1
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struct blsp_spi {
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unsigned int spi_config;
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unsigned int io_control;
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unsigned int error_flags;
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unsigned int error_flags_en;
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unsigned int qup_config;
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unsigned int qup_error_flags;
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unsigned int qup_error_flags_en;
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unsigned int qup_operational;
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unsigned int qup_io_modes;
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unsigned int qup_state;
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unsigned int qup_input_fifo;
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unsigned int qup_output_fifo;
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unsigned int qup_mx_input_count;
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unsigned int qup_mx_output_count;
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unsigned int qup_mx_read_count;
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unsigned int qup_mx_write_count;
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unsigned int qup_sw_reset;
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unsigned int qup_op_mask;
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unsigned int qup_deassert_wait;
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};
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static const struct blsp_spi spi_reg[] = {
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/* BLSP0 registers for SPI interface */
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{
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BLSP0_SPI_CONFIG_REG,
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BLSP0_SPI_IO_CONTROL_REG,
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BLSP0_SPI_ERROR_FLAGS_REG,
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BLSP0_SPI_ERROR_FLAGS_EN_REG,
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BLSP0_QUP_CONFIG_REG,
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BLSP0_QUP_ERROR_FLAGS_REG,
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BLSP0_QUP_ERROR_FLAGS_EN_REG,
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BLSP0_QUP_OPERATIONAL_REG,
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BLSP0_QUP_IO_MODES_REG,
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BLSP0_QUP_STATE_REG,
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BLSP0_QUP_INPUT_FIFOc_REG(0),
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BLSP0_QUP_OUTPUT_FIFOc_REG(0),
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BLSP0_QUP_MX_INPUT_COUNT_REG,
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BLSP0_QUP_MX_OUTPUT_COUNT_REG,
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BLSP0_QUP_MX_READ_COUNT_REG,
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BLSP0_QUP_MX_WRITE_COUNT_REG,
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BLSP0_QUP_SW_RESET_REG,
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BLSP0_QUP_OPERATIONAL_MASK,
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BLSP0_SPI_DEASSERT_WAIT_REG,
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},
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/* BLSP1 registers for SPI interface */
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{
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BLSP1_SPI_CONFIG_REG,
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BLSP1_SPI_IO_CONTROL_REG,
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BLSP1_SPI_ERROR_FLAGS_REG,
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BLSP1_SPI_ERROR_FLAGS_EN_REG,
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BLSP1_QUP_CONFIG_REG,
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BLSP1_QUP_ERROR_FLAGS_REG,
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BLSP1_QUP_ERROR_FLAGS_EN_REG,
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BLSP1_QUP_OPERATIONAL_REG,
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BLSP1_QUP_IO_MODES_REG,
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BLSP1_QUP_STATE_REG,
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BLSP1_QUP_INPUT_FIFOc_REG(0),
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BLSP1_QUP_OUTPUT_FIFOc_REG(0),
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BLSP1_QUP_MX_INPUT_COUNT_REG,
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BLSP1_QUP_MX_OUTPUT_COUNT_REG,
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BLSP1_QUP_MX_READ_COUNT_REG,
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BLSP1_QUP_MX_WRITE_COUNT_REG,
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BLSP1_QUP_SW_RESET_REG,
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BLSP1_QUP_OPERATIONAL_MASK,
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},
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};
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#define SUCCESS 0
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#define FAILURE 1
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#define DUMMY_DATA_VAL 0
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#define TIMEOUT_CNT 100
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#define SPI_BITLEN_MSK 0x07
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#define WRITE 0
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#define READ 1
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struct ipq_spi_slave {
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struct spi_slave slave;
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const struct blsp_spi *regs;
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unsigned int core_state;
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unsigned int mode;
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unsigned int initialized;
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unsigned long freq;
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unsigned char use_dma;
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};
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static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct ipq_spi_slave, slave);
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}
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/* QUP BAM related defines */
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#define DATA_CONSUMER_PIPE_INDEX 0
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#define DATA_PRODUCER_PIPE_INDEX 1
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/* QUP0 BAM pipe numbers */
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#define QUP0_DATA_CONSUMER_PIPE 12
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#define QUP0_DATA_PRODUCER_PIPE 13
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/* QUP1 BAM pipe numbers */
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#define QUP1_DATA_CONSUMER_PIPE 6
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#define QUP1_DATA_PRODUCER_PIPE 7
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/* QUP0 BAM pipe groups */
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#define QUP0_DATA_PRODUCER_PIPE_GRP 0
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#define QUP0_DATA_CONSUMER_PIPE_GRP 0
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/* QUP1 BAM pipe groups */
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#define QUP1_DATA_PRODUCER_PIPE_GRP 0
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#define QUP1_DATA_CONSUMER_PIPE_GRP 0
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#define NO_OF_QUPS 2
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/* QUP EE */
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#define QUP_SPI_EE 0
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/* QUP max desc length. */
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#define QUP_SPI_MAX_DESC_LEN 0xFFFF
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#define QUP_SPI_BAM_THRESHOLD 16
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#define SPI_MAX_TRFR_BTWN_RESETS ((64 * 1024) - 16) /* 64KB - 16byte */
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#define SPI_BAM_MAX_DESC_NUM 32
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#define QUP_BAM_DATA_FIFO_SIZE 32
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static struct bam_instance bam;
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struct bam_desc qup_spi_data_desc_fifo[QUP_BAM_DATA_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE)));
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#endif /* _IPQ_SPI_BAM_H_ */
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