Lokesh Vutla ea8eff1fe0 arm: dra7xx: clock: Add the dplls data ... A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>		2013-03-11 11:06:11 -04:00
..
arm	arm: dra7xx: clock: Add the dplls data	2013-03-11 11:06:11 -04:00
avr32	avr32: Use generic global_data	2013-02-04 09:05:45 -05:00
blackfin	blackfin: Use generic global_data	2013-02-04 09:05:45 -05:00
m68k	m68k: Use generic global_data	2013-02-04 09:05:45 -05:00
microblaze	Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze	2013-02-04 09:14:22 -05:00
mips	MIPS: board.c: remove manual relocation of env_name_spec	2013-02-15 18:00:04 +01:00
nds32	nds32: Use generic global_data	2013-02-04 09:05:46 -05:00
nios2	Clean up libfdt.h includes	2013-02-08 22:32:38 -05:00
openrisc	openrisc: Use generic global_data	2013-02-04 09:05:46 -05:00
powerpc	Clean up libfdt.h includes	2013-02-08 22:32:38 -05:00
sandbox	sandbox: Use generic global_data	2013-02-04 09:05:46 -05:00
sh	sh: Use generic global_data	2013-02-04 09:05:46 -05:00
sparc	sparc: Use generic global_data	2013-02-04 09:05:46 -05:00
x86	x86: Remove unused real mode code	2013-02-14 20:19:03 -08:00
.gitignore	update include/asm/ gitignore after move	2010-05-07 00:17:30 +02:00