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LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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| .. | ||
| arm_ddr_gen3.c | ||
| ctrl_regs.c | ||
| ddr1_dimm_params.c | ||
| ddr2_dimm_params.c | ||
| ddr3_dimm_params.c | ||
| ddr4_dimm_params.c | ||
| fsl_ddr_gen4.c | ||
| fsl_mmdc.c | ||
| interactive.c | ||
| Kconfig | ||
| lc_common_dimm_params.c | ||
| main.c | ||
| Makefile | ||
| mpc85xx_ddr_gen1.c | ||
| mpc85xx_ddr_gen2.c | ||
| mpc85xx_ddr_gen3.c | ||
| mpc86xx_ddr.c | ||
| options.c | ||
| util.c | ||