mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-14 21:10:27 +01:00
b979e35230
The board uses T-topology for the four x16 DRAM chips, so remove the write-leveling from the SPL as that is only usefly on fly-by topology and can be harmful on T-topology. Also update the DRAM timing with values from calibration on multiple boards. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> |
||
|---|---|---|
| .. | ||
| dh_imx6.c | ||
| dh_imx6_spl.c | ||
| Kconfig | ||
| MAINTAINERS | ||
| Makefile | ||